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參數(shù)資料
| 型號(hào)： | AK4633 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| 中文描述： | 16位單聲道編解碼器ALC的 |
| 文件頁(yè)數(shù)： | 28/82頁(yè) |
| 文件大?。?/td> | 688K |
| 代理商： | AK4633 |
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ASAHI KASEI
[AK4633]
MS0447-E-03
2006/04
- 28 -
When PLL2 bit is
“
0
”
(PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2 bits
(Table 6).
FS3 bit
FS2 bit
FS1 bit
Mode
FS0 bit
Sampling Frequency
Range
7.35kHz
≤
fs
≤
12kHz
12kHz < fs
≤
24kHz
24kHz < fs
≤
48kHz
N/A
0
1
2
0
0
1
0
1
0
Don’t care
Don’t care
Don’t care
Others
Don’t care
Don’t care
Don’t care
Default
Others
Table 6. Setting of Sampling Frequency at PLL2 bit =
“
0
”
and PMPLL bit =
“
1
”
PLL Unlock State
1) PLL Master Mode (PMPLL bit =
“
1
”
, M/S bit =
“
1
”
)
In this mode, after PMPLL bit =
“
0
”
“
1
”
and until PLL locked ,
“
L
”
are output from BICK and FCK pins and invalid
frequency clock is output from MCKO pin when MCKO bit is
“
1
”
. If MCKO bit is
“
0
”
,
“
L
”
is output from MCKO pin.
( Table 7)
In case that sampling frequency is changed, setting PMPLL bit to
“
0
”
once a time could be prevent BICK and FCK pins
output to
“
L
”
from unstable clocks.
MCKO pin
PLL State
MCKO bit =
“
0
”
MCKO bit =
“
1
”
After that PMPLL bit
“
0
”
“
1
”
“
L
”
Output
PLL Unlock
“
L
”
Output
PLL Lock
“
L
”
Output
256fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit =
“
1
”
, M/S bit =
“
1
”
)
2) PLL Slave Mode (PMPLL bit =
“
1
”
, M/S bit =
“
0
”
)
In this mode, an invalid clock is output from MCKO pin after PMPLL bit =
“
0
”
“
1
”
or sampling frequency is changed.
After that, 256fs clock is output from MCKO pin while PLL is locked. However, the normal data couldn’t output from
ADC and DAC while PLL is unlocked. For DAC, the output signal should be muted by setting
“
0
”
to DACA and DACM
bits in Addr=02H.
BICK pin
FCK pin
Invalid
Invalid
Invalid
“
L
”
Output
See Table 9
Invalid
“
L
”
Output
1fs Output
MCKO pin
PLL State
MCKO bit =
“
0
”
“
L
”
Output
“
L
”
Output
“
L
”
Output
MCKO bit =
“
1
”
Invalid
Invalid
256fs Output
After that PMPLL bit
“
0
”
“
1
”
PLL Unlock
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit =
“
1
”
, M/S bit =
“
0
”
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4640 | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4640VG | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4640VN | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4642EN | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4643EN | Stereo CODEC with MIC/HP/RCV/SPK-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4633ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:LOW COST MONO CODEC WITH SPK A |
| AK4633VN | 制造商:AKM 制造商全稱:AKM 功能描述:16bit mono CODEC with MIC/SPK amplifier. |
| AK4633VNP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:LOW COST MONO CODEC WITH SPK A |
| AK4634 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4635 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP |
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