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參數(shù)資料
| 型號： | AK4632 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16-Bit ツヒ Mono CODEC with ALC & MIC/SPK/Video-AMP |
| 中文描述： | 16位ツヒALC的單聲道編解碼器 |
| 文件頁數(shù)： | 61/70頁 |
| 文件大小： | 639K |
| 代理商： | AK4632 |
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ASAHI KASEI
[AK4632]
MS0396-E-00
2005/06
- 61 -
MIC Input Recording
FS3-0 bits
(Addr:05H,
D5,D2-0)
MIC Control
(Addr:02H, D2-0)
PMADC bit
(Addr:00H, D0)
PMMIC bit
(Addr:00H, D1)
ADC Internal
State
XXX
XXXX
001
X1X
Power Down
Initialize Normal State Power Down
1059 / fs
(1)
(2)
(6)
(7)
ALC1 State
ALC1 Enable
ALC1 Disable
ALC1 Disable
(5)
ALC1 Control 1
(Addr:06H)
XXH
00H
(3)
ALC1 Control 2
(Addr:08H)
XXH
47H
(4)
ALC1 Control 3
(Addr:07H)
XXH
61H or 21H
Example:
PLL Master Mode
Audio I/F Format:DSP Mode, BCKP=MSBS=“0”
Sampling Frequency:8kHz
Pre MIC AMP:+20dB
MIC Power On
ALC1 setting:Refer to Figrure 29
ALC2 bit=“1”(default)
(2) Addr:02H, Data:07H
(3) Addr:06H, Data:00H
(1) Addr:05H, Data:00H
(4) Addr:08H, Data:47H
(5) Addr:07H, Data:61H
(6) Addr:00H, Data:43H
Recording
(7) Addr:00H, Data:40H
Figure 50. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at s=8kHz. If the parameter of the ALC1 is changed, please refer to
“
Figure 31. Registers set-up sequence at the ALC1 operation
“
At first, clocks should be supplied according to
“
Clock Set Up
”
sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK4632 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 02H)
(3) Set up Timer Select for ALC1 (Addr: 06H)
(4) Set up REF value for ALC1 (Addr: 08H)
(5) Set up LMTH, RATT, LMAT1-0 and ALC1 bits (Addr: 07H)
(6) Power Up MIC and ADC: PMMIC bit = PMADC bit =
“
0
”
→
“
1
”
The initialization cycle time of ADC is 1059/fs=133ms@fs=8kHz.
After the ALC1 bit is set to
“
1
”
and MIC block is powered-up, the ALC1 operation starts from IPGA default
value (0dB).
(7) Power Down MIC and ADC: PMMIC bit = PMADC bit =
“
1
”
→
“
0
”
When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping
“
1
”
. The ALC1 operation
is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also changed
when the sampling frequency is changed, it should be done after the AK4632 goes to the manual mode (ALC1 bit
=
“
0
”
) or MIC block is powered-down (PMMIC bit =
“
0
”
). IPGA gain is reset when PMMIC bit is
“
0
”
, and then
IPGA operation starts from the default value when PMMIC bit is changed to
“
1
”
.
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PDF描述 |
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| AK4633VN | 16bit mono CODEC with MIC/SPK amplifier. |
| AK4633 | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4640 | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4632VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Mono CODEC with ALC & MIC/SPK/Video-AMP |
| AK4633 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4633ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:LOW COST MONO CODEC WITH SPK A |
| AK4633VN | 制造商:AKM 制造商全稱:AKM 功能描述:16bit mono CODEC with MIC/SPK amplifier. |
| AK4633VNP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:LOW COST MONO CODEC WITH SPK A |
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