
ASAHI KASEI
[AK4632]
MS0396-E-00
2005/06
- 33 -
[3] Example of ALC1 Operation
Table 15 shows the example of the ALC1 setting. In case of this example, ALC1 operation starts from 0dB.
fs=8kHz
fs=16kHz
Data
1
00
0
01
Register Name Comment
Data
1
00
0
00
Operation
-4dBFS
Don’t use
Enable
16ms
Operation
-4dBFS
Don’t use
Enable
16ms
LMTH
LTM1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter operation period at ZELM = 1
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
IPGA gain at the start of ALC1 operation
Limiter ATT Step
Recovery GAIN Step
ALC1 Enable bit
WTM1-0
00
16ms
01
16ms
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
47H
10H
00
0
1
+27.5dB
0dB
1 step
1 step
Enable
47H
10H
00
0
1
+27.5dB
0dB
1 step
1 step
Enable
Table 15. Examples of the ALC1 Setting
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit =
“
0
”
or PMMIC bit =
“
0
”
.
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
When setting IPGA gain at the start of ALC1 operation, IPGA6-0 bits should be set while PMMIC bit is
“
1
”
and ALC1 bit
is
“
0
”
. When PMMIC bit =
“
1
”
, IPGA6-0 bits value aren’t reflected to IPGA. When ALC1 bit is changed from
“
1
”
to
“
0
”
,
IPGA holds the last gain value set automatically by ALC1 operation.
Manual Mode
* The value of IPGA should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF6-0)
WR (IPGA6-0)
ALC1 Operation
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
ALC2 bit = “1” (default)
(1) Addr=06H, Data=00H
(2) Addr=08H, Data=47H
(4) Addr=07H, Data=61H
(3) Addr=09H, Data=10H
Note : WR : Write
Figure 31. Registers set-up sequence at the ALC1 operation