參數(shù)資料
型號: AK4589VQ
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 2/8-Channel Audio CODEC with DIR
中文描述: 2/8-Channel音頻編解碼器迪爾
文件頁數(shù): 68/76頁
文件大?。?/td> 838K
代理商: AK4589VQ
ASAHI KASEI
[AK4589]
MS0339-E-00
2004/09
- 68 -
(2) I
2
C bus control mode (I2C pin = “H”)
AK4589 supports the standard-mode I
2
C-bus (max: 100kHz). Then AK4589 does not support a fast-mode I
2
C-bus
system (max: 400kHz).
(2)-1 Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4589 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave
device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition
generated by the master device.
(2)-1-1 Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
CHANGE
OF DATA
ALLOWED
Figure 41. Data transfer
(2)-1-2 START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
STOP CONDITION
START CONDITION
Figure 42. START and STOP conditions
相關(guān)PDF資料
PDF描述
AK4591 24bit 4ch ADC + 24bit 6ch DAC
AK4620A 24 BIT 192KHZ AUDIO CODEC WITH IPGA
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AK4620BVF 24-Bit 192kHz Audio CODEC with IPGA
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