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參數(shù)資料
| 型號： | AK4589VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 2/8-Channel Audio CODEC with DIR |
| 中文描述： | 2/8-Channel音頻編解碼器迪爾 |
| 文件頁數(shù)： | 36/76頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AK4589VQ |
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ASAHI KASEI
[AK4589]
MS0339-E-00
2004/09
- 36 -
Power ON/OFF Sequence
The ADC and DACs of AK4589 are placed in the power-down mode by bringing PDN pin “L” and both digital filters
are reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode,
the analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be done after power-up.
In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data,
SDTO1 becomes available after 522 cycles of LRCK1 clock. In case of the DAC, an analog initialization cycle starts
after exiting the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 14 shows
the sequences of the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWADN and PWDAN bits. And DAC1-4 can be
power-down individually by PD1-4 bits. In this case, the internal register values are not initialized. When PWADN bit
= “0”, SDTO1 pin goes to “L”. When PWDAN bit = “0” and PD1-4 bits = “0”, the analog outputs go to VCOM voltage
and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted externally if the click
noise influences system application.
Power
ADC Internal
State
PDN pin
Clock In
MCLK,LRCK1,
BICK1
ADC In
(Analog)
ADC Out
(Digital)
DAC Internal
State
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(9)
DZF1/DZF2
Power-down
Don’t care
GD
“0”data
Power-down
“0”data
GD
(3)
(3)
(4)
(6)
(7)
(8)
522/fs
Init Cycle
Normal Operation
(1)
GD
Normal Operation
GD
(5)
(6)
516/fs
Init Cycle
(2)
10
～
11/fs (10)
Mute ON
“0”data
“0”data
Don’t care
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK1 and LRCK1) are stopped, the AK4589 should be in the power-down
mode.
(8) DZF1-2 pins are “L” in the power-down mode (PDN pin = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF= “L” for 10
～
11/fs after PDN= “
↑
”.
Figure 14. Power-down/up sequence example
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