參數(shù)資料
型號(hào)： AK4589VQ
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi)： Codec
英文描述： 2/8-Channel Audio CODEC with DIR
中文描述： 2/8-Channel音頻編解碼器迪爾
文件頁(yè)數(shù)： 51/76頁(yè)
文件大小： 838K
代理商： AK4589VQ
ASAHI KASEI
[AK4589]
MS0339-E-00
2004/09
- 51 -
Error Handling
There are the following eight events that make INT0/1 pins “H”. INT0/1 pins show the status of following conditions.
1. UNLOCK: “1” when the PLL loses lock.
The AK4589 loses lock when the distance between two preambles is not correct or when those
preambles are not correct.
2. PAR: “1” when parity error or biphase coding error is detected, and keeps “1” until this register is read.
Updated every sub-frame cycle. Reading this register resets itself.
3. AUTO: “1” when Non-PCM bitstream is detected.
Updated every 4096 frames cycle.
4. DTSCD: “1” when DTS-CD bitstream is detected.
Updated every DTS-CD sync cycle.
5. AUDION: “1” when the “AUDIO” bit in recovered channel status indicates “1”.
Updated every block cycle.
6. PEM: “1” when “PEM” in recovered channel status indicates “1”.
Updated every block cycle.
7. QINT: “1” when Q-subcode differ from old one, and keeps “1” until this register is read.
Updated every sync code cycle for Q-subcode. Reading this register resets itself.
8. CINT: “1” when received C bits differ from old one, and keeps “1” until this register is read.
Updated every block cycle. Reading this register resets itself.
Both INT0/1 are fixed to “L” when the PLL is off (CM1,0= “01”). Once the INT0 pin goes to “H”, this pin holds “H” for
1024/fs cycles (this value can be changed by EFH0/1 bits) after those events are removed. INT1 pin goes to “L” at the
same time when those events are removed. Each INT0/1 pins can mask those eight events individually. Once PAR, QINT
and CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4589 loses lock,
registers regarding C-bit or U-bits are not initialized and keep previous value.
INT0/1 pin output the ORed signal among those eight events. However, each events can be masked by each mask bits.
When each bit masks those events, the event does not affect INT0/1 pins operation (those mask do not affect those
registers (UNLOCK, PAR, etc.) themselves. Once INT0 pin goes “H”, it maintains “H” for 1024/fs cycles (this value can
be changed by EFH0-1 bits) after the all events are removed. Once those PAR, QINT or CINT bit goes “1”, it holds “1”
until reading those registers. While the AK4589 loses lock, the channel status an Q-subcode bits are not updated and
holds the previous data. At initial state, INT0 outputs the ORed signal between UNLOCK and PAR, INT1 outputs the
ORed signal among AUTO, DTSCD and AUDION.
Register
UNLOCK
PAR
AUTO
DTSCD
AUDION
PEM
1
x
x
x
x
0
1
x
x
x
0
0
1
x
x
0
0
x
1
x
0
0
x
x
1
0
0
x
x
x
0
0
x
x
x
0
0
x
x
x
Table 28. Error Handling
Pin
QINT
x
x
x
x
x
x
1
x
CINT
x
x
x
x
x
x
x
1
SDTO2
“L”
Previous Data
Output
Output
Output
Output
Output
Output
V
“L”
Output
Output
Output
Output
Output
Output
Output
TX
Output
Output
Output
Output
Output
Output
Output
Output
x
x
x
x
x
1
x
x
相關(guān)PDF資料
PDF描述
AK4591 24bit 4ch ADC + 24bit 6ch DAC
AK4620A 24 BIT 192KHZ AUDIO CODEC WITH IPGA
AK4620AVF 24 BIT 192KHZ AUDIO CODEC WITH IPGA
AK4620B 24-Bit 192kHz Audio CODEC with IPGA
AK4620BVF 24-Bit 192kHz Audio CODEC with IPGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4591 制造商:AKM 制造商全稱(chēng):AKM 功能描述:24bit 4ch ADC + 24bit 6ch DAC
AK4591VQ 制造商:AKM 制造商全稱(chēng):AKM 功能描述:??￥???????????ˉ??????24bit 4ch ADC 24bit 6ch DAC
AK45C 制造商:ASTEC 制造商全稱(chēng):Astec America, Inc 功能描述:36 Vdc to 75 Vdc Inputs, 100 W
AK45C048HS002 制造商:ASTEC 制造商全稱(chēng):Astec America, Inc 功能描述:36 Vdc to 75 Vdc Inputs, 100 W
AK45C048HS002-6 制造商:ASTEC 制造商全稱(chēng):Astec America, Inc 功能描述:36 Vdc to 75 Vdc Inputs, 100 W
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*