參數(shù)資料
型號(hào)： AK4538VN
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 16Bit DS CODEC with MIC/HP/SPK-AMP
中文描述： 16位副編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁(yè)數(shù)： 64/70頁(yè)
文件大?。?/td> 485K
代理商： AK4538VN
ASAHI KASEI
[AK4538]
MS0198-E-01
2003/5
- 64 -
n
MIC Input Recording
FS2-0 bits
(Addr:05H, D7-5)
MIC Control
(Addr:07H, D2-0)
PMADC bit
(Addr:00H, D0)
PMMIC bit
(Addr:00H, D1)
ADC Internal
State
XXX
000
00001
XX1XX
Power Down
Initialize Normal State Power Down
2081 / fs
(1)
(2)
(6)
(7)
ALC1 State
ALC1 Enable
ALC1 Disable
ALC1 Disable
(5)
ALC1 Control 1
(Addr:08H)
XXH
00H
(3)
ALC1 Control 2
(Addr:0AH)
XXH
47H
(4)
ALC1 Control 3
(Addr:09H)
XXH
61H or 21H
Example :
X’tal and PLL are used.
Sampling Frequency : 8kHz
Mic Select : Internal Mic
Pre Mic AMP : +20dB
MIC Power On
ALC1 setting : Refer to Figure 9
(1) Addr:05H, Data:E0H
(3) Addr:08H, Data:00H
(4) Addr:0AH, Data:47H
(5) Addr:09H, Data:61H
(2) Addr:07H, Data:0DH
(6) Addr:00H, Data 83H
Recording
(7) Addr:00H, Data 80H
Figure 53. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=8kHz. If the parameter of the ALC1 is changed, please refer to
“Figure 21. Registers set-up sequence at the ALC1 operation.”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits). When the AK4538 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 07H)
(3) Set up Timer Select for ALC1 (Addr: 08H)
(4) Set up REF value for ALC1 (Addr: 0AH)
(5) Set up LMTH, RATT, LMAT1-0, ALC1 bits (Addr: 09H)
(6) Power Up MIC and ADC: PMMIC bit = PMADC bit = “0”
→
“1”
The initialization cycle time of ADC is 2081/fs=47.2ms@fs=44.1kHz.
After the ALC1 bit is set to “1” and MIC block is powered-up, the ALC1 operation starts from IPGA initial
value (0dB).
(7) Power Down MIC and ADC: PMMIC bit = PMADC bit = “1”
→
“0”
When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping “1”. The ALC1
operation is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also
changed when the sampling frequency is changed, it should be done after the AK4538 goes to the manual mode
(ALC1 bit = “0”) or MIC block is powered-down (PMMIC bit = “0”). IPGA gain is reset when PMMIC bit is
“0”, and then IPGA operation starts from the default value when PMMIC is changed to “1”.
相關(guān)PDF資料
PDF描述
AK4541VQ AC’97 Rev 2.1 Multimedia Audio CODEC
AK4541 AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543 AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543VQ AC’97 Rev 2.1 Multimedia Audio CODEC
AK4544A AC97 MULTIMEDIA AUDIO CODEC WITH SRC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4541 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4541VQ 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543VQ 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4544 制造商:AKM 制造商全稱:AKM 功能描述:AC97 MULTIMEDIA AUDIO CODEC WITH SRC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*