參數(shù)資料
型號(hào): AK4538VN
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16Bit DS CODEC with MIC/HP/SPK-AMP
中文描述: 16位副編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 60/70頁
文件大?。?/td> 485K
代理商: AK4538VN
ASAHI KASEI
[AK4538]
MS0198-E-01
2003/5
- 60 -
n
Clock Set up
When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCLK, BICK and LRCK) must be supplied.
1. When X'tal is used in PLL mode. (Slave mode)
MCKPD bit
(Addr:01H, D7)
BICK, LRCK
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
XX
00
40ms(max)
Output
Input
(1)
20ms(typ)
(2)
(3)
(4)
(5)
(6)
E xam p le :
Audio I/F Format : I
2
S
B ICK frequency at M a ster Mode : 64fs
Input Master C lock S e lect at PLL Mode : 11.2896M H z
O utput M aster C lock Fre q uency : 64fs
(1) Addr:01H, Data:40H
(2) Addr:01H, Data:60H
(3) Addr:04H, Data 4AH
(4) MCKO output starts
(5) BICK and LRCK input start
(6) Addr:04H, Data 6AH
Figure 48. Clock Set Up Sequence(1)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1”
“0” and power-up the X’tal oscillator: PMXTL bit =
“0”
“1”
(2) Power-up the PLL : PMPLL bit = “0”
“1”
The PLL should be powered-up after the X’tal oscillator becomes stable. If X'tal and PLL are powered-up at the
same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit= “1”. This
time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0”
“1”.
(3) Enable MCKO output : MCKO bit = “0”
“1”
(4) MCKO is output after PLL becomes stable.
(5) Input BICK and LRCK synchronized with the MCKO output.
(6) Set the MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
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