參數(shù)資料
型號: AK4536VN
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16-Bit Mono CODEC with ALC & MIC/SPK-AMP
中文描述: 16位單聲道編解碼器ALC的
文件頁數(shù): 51/59頁
文件大?。?/td> 403K
代理商: AK4536VN
ASAHI KASEI
[AK4536]
MS0174-E-00
2002/09
- 51 -
2. When an external master clock is used in PLL & Master mode.
MCKPD bit
(Addr:01H, D2)
BICK, FCK
PMXTL bit
(Addr:01H, D0)
PMPLL bit
(Addr:01H, D5)
40msec(max)
Output
(1)
(4)
(7)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
(2)
(3)
MCKI
(6)
"L"
(5)
"L" or "H"
Input
M/S bit
(Addr:01H, D3)
1msec max)
(8)
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKI pin: CMOS Level
Sampling Frequency:8kHz
(1) Power Supply & PDN pin = “L”
à
“H”
(3)Addr:00H, Data:40H
(2)Addr:01H, Data:0CH
Addr:04H, Data:48H
Addr:05H, Data:00H
(4)Addr:01H, Data:09H
BICK and FCK output
Figure 35. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDN pin “L”
à
“H”
“L” time (1) of 150ns or more is needed to reset the AK4536.
(2) DIF1-0, PLL2-0, FS2-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”
à
“1”
VCOM should first be powered up before the other block operates.
(4) Release the pulled-down of the XTI pin: MCKPD bit = “1”
“0”
Power Down X’al: PMXTL bit = “0”
(5) When MCKI pin is input by AC coupling: PMXTL bit = “1”
When MCKI pin is input by CMOS Level: PMXTL bit = “0”
(6) When PMPLL bit changes from “0” to “1”, the PLL starts after the clocks is supplied to MCKI pin. The PLL lock
time is 40ms(max).
(7) The AK4536 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of the
block which a clock is necessary for becomes possible.
(8) The irregular frequencies are output from FCK and BICK pins in this section.
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