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參數(shù)資料
| 型號： | AK4536VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| 中文描述： | 16位單聲道編解碼器ALC的 |
| 文件頁數(shù)： | 25/59頁 |
| 文件大小： | 403K |
| 代理商： | AK4536VN |
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ASAHI KASEI
[AK4536]
MS0174-E-00
2002/09
- 25 -
n
System Reset
Upon power-up, reset the AK4536 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their
initial values.
The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle
time is 1059/fs, or 133ms@fs=8kHz. During the initialization cycle, the ADC digital data outputs of both channels are
forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete.
The DAC does not require an initialization cycle.
n
Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits. (See Table 13) In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and
BICK are output from AK4536 in master mode, but must be input to AK4536 in slave mode.
In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK.
When BCKP bit is “1”, SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK.
MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK.
MSBS bit
BCKP bit
0
0
0
1
1
0
1
1
Table 12. Relationship MSBS and BCKP bits between data I/O timing
In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit,
1 at 16bit data is converted to
1 at 8-bit
data. And when the DAC playbacks this 8-bit data,
1 at 8-bit data will be converted to
256 at 16-bit data and this is a
large offset. This offset can be removed by adding the offset of 128 to 16-bit data before converting to 8-bit data.
Mode
DIF1
DIF0
SDTO (ADC)
SDTI (DAC)
Data Input/Output Timing
Figure 21
Figure 23
Figure 22
Figure 24
BICK
Figure
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
0
0
0
DSP Mode
DSP Mode
≥
16fs
1
2
3
0
1
1
1
0
1
MSB justified
MSB justified
I
2
S compatible
Table 13. Audio Interface Format
MSB justified
MSB justified
I
2
S compatible
≥
32fs
≥
32fs
≥
32fs
Default
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| AK4537 | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VN | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4538 | 16Bit DS CODEC with MIC/HP/SPK-AMP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4537 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK4537VNP-L |
| AK4538 | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4538VN | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP |
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