參數(shù)資料
型號： AK4397
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： High Performance Premium 32-Bit DAC
中文描述： 優(yōu)質(zhì)高性能32位DAC
文件頁數(shù)： 32/37頁
文件大?。?/td> 513K
代理商： AK4397
[AK4397]
MS0616-E-00
2007/05
- 32 -
Analog Ground
Digital Ground
System
Controller
DVDD
N
1
PDN
4
2
BICK
3
SDATA
4
LRCK
5
CSN
6
CAD0
7
CCLK
8
CDTI
9
DFS0
10
DIF1
11
D
1
33
AOUTLN
A
1
1
1
1
1
1
1
2
2
2
N
P
D
D
C
N
N
N
N
A
32
VSS2
31
VDDL
30
VREFHL
29
VREFLL
28
NC
27
VREFLR
26
VREFHR
25
VDDR
24
VSS1
23
AOUTRN
V
M
A
V
N
N
N
N
N
A
Figure 16. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD,
respectively. AVDD, VDDL/R is supplied from analog supply in system and DVDD is supplied from digital supply in
system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from the point with low impedance
of regulator etc. The power up sequence between AVDD, VDDL/R and DVDD is not critical.
VSS1-4 must be
connected to the same analog ground plane.
Decoupling capacitors for high frequency should be placed as near
as possible.
2. Voltage Reference
The differential Voltage between VREFHL/R and VREFLL/R set the analog output range. VREFHL/R pin is normally
connected to AVDD and VREFLL/R pin is normally connected to VSS. VREFHL/R and VREFLL/R should be
connected with a 0.1μF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10μF parallel
with a 0.1μF ceramic capacitor attached between VCOM and VSS eliminates the effects of high frequency noise. No load
current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFHL/R,
VREFLL/R and VCOM pins in order to avoid unwanted coupling into the AK4397.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R
VREFLL/R = 5V) centered around
VCOM. The differential outputs are summed externally, V
AOUT
= (AOUT+)
(AOUT
) between AOUT+ and AOUT
.
If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R
VREFLL/R = 5V). The bias voltage of the
external summing circuit is supplied externally. The input data format is 2's complement. The output voltage (V
AOUT
) is a
positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal V
AOUT
is 0V for
000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 17 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 18 shows an example of differential outputs and LPF circuit example by three op-amps.
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