參數(shù)資料
型號: AK4397
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: High Performance Premium 32-Bit DAC
中文描述: 優(yōu)質(zhì)高性能32位DAC
文件頁數(shù): 12/37頁
文件大?。?/td> 513K
代理商: AK4397
[AK4397]
MS0616-E-00
2007/05
- 12 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD=VDDL/R=4.75
5.25V, DVDD=4.75
5.25V)
Parameter
Master Clock Timing
Frequency
Duty Cycle
LRCK Frequency
(Note 17)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “
” to LRCK Edge (Note 18)
LRCK Edge to BICK “
” (Note 18)
SDATA Hold Time
SDATA Setup Time
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 19)
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “
” to CCLK “
CCLK “
” to CSN “
Reset Timing
PDN Pulse Width (Note 20)
Note 17. When the normal/double/quad speed modes are switched, AK4397 should be reset by PDN pin or RSTN bit.
Note 18. BICK rising edge must not occur at the same time as LRCK edge.
Note 19. DSD data transmitting device must meet this time.
Note 20. The AK4397 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change,
the AK4397 should be reset by RSTN bit.
Symbol
fCLK
dCLK
fsn
fsd
fsq
Duty
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
tDCK
tDCKL
tDCKH
tDDD
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tPD
min
7.7
40
30
54
108
45
1/128fn
1/64fd
1/64fq
30
30
20
20
20
20
1/64fs
160
160
20
200
80
80
50
50
150
50
50
150
typ
max
41.472
60
54
108
216
55
20
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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