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參數(shù)資料
| 型號： | AK4397 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | High Performance Premium 32-Bit DAC |
| 中文描述： | 優(yōu)質(zhì)高性能32位DAC |
| 文件頁數(shù)： | 16/37頁 |
| 文件大?。?/td> | 513K |
| 代理商： | AK4397 |
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[AK4397]
MS0616-E-00
2007/05
- 16 -
OPERATION OVERVIEW
■
D/A Conversion Mode
In serial mode, the AK4397 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4397
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4397 performs for
only PCM data.
D/P bit
0
1
Table 1. PCM/DSD Mode Control
■
System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4397, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. When external clocks are changed, the AK4397 should be reset by PDN pin or RSTN bit.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4397 is in normal operation
mode (PDN pin = “H”). If these clocks are not provided, the AK4397 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4397 should be in the power-down mode
(PDN pin = “L”) or in the reset mode (RSTN bit = “0”). After exiting reset (PDN pin = “L”
→
“H”) at power-up etc., the
AK4397 is in power-down mode until MCLK is supplied.
(1) Parallel Mode (P/S pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
MCLK frequency is detected automatically and the sampling speed is set by DFS0 pin (Table 2). The MCLK frequency
corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. When DFS0 pin is changed,
the AK4397 should be reset by PDN pin. Quad speed mode is not supported in this mode.
DFS0 pin
Sampling Rate (fs)
L
Normal Speed Mode
H
Double Speed Mode
Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode)
LRCK
MCLK (MHz)
fs
128fs
192fs
256fs
384fs
32.0kHz
N/A
N/A
8.1920
12.2880
44.1kHz
N/A
N/A
11.2896
16.9344
48.0kHz
N/A
N/A
12.2880
18.4320
88.2kHz
11.2896
16.9344
22.5792
33.8688
96.0kHz
12.2880
18.4320
24.5760
36.8640
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)
Interface
PCM
DSD
30kHz
～
54kHz
54kHz
～
108kHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
512fs
16.3840
22.5792
24.5760
N/A
N/A
768fs
24.5760
33.8688
36.8640
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
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