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參數(shù)資料
| 型號： | AK4397 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | High Performance Premium 32-Bit DAC |
| 中文描述： | 優(yōu)質(zhì)高性能32位DAC |
| 文件頁數(shù)： | 26/37頁 |
| 文件大?。?/td> | 513K |
| 代理商： | AK4397 |
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[AK4397]
MS0616-E-00
2007/05
- 26 -
■
Reset Function
When RSTN bit = “0”, the AK4397’s digital section is powered down but the internal register values are not initialized.
The analog outputs go to VCOM voltage and DZF pins of both channels go to “H”. Figure 13 shows the example of reset
by RSTN bit.
RSTN bit
Internal
State
Digital Block
P
d
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(1)
(3)
DZFL/DZFR
(3)
(1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN Timing
2~3/fs (6)
3~4/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges (“
↑
↓
”) of the internal timing of RSTN bit.
This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “0”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
Figure 13. Reset sequence example
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