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參數(shù)資料
| 型號(hào)： | AK4397 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | High Performance Premium 32-Bit DAC |
| 中文描述： | 優(yōu)質(zhì)高性能32位DAC |
| 文件頁(yè)數(shù)： | 18/37頁(yè) |
| 文件大小： | 513K |
| 代理商： | AK4397 |
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[AK4397]
MS0616-E-00
2007/05
- 18 -
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 8) and DFS1-0 bits are ignored. The MCLK
frequency corresponding to each sampling speed should be provided (Table 9).
MCLK
1152fs
512fs
768fs
256fs
384fs
128fs
192fs
Table 8. Sampling Speed (Auto Setting Mode @Serial Mode)
LRCK
MCLK (MHz)
fs
128fs
192fs
256fs
384fs
32.0kHz
N/A
N/A
N/A
N/A
44.1kHz
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
22.5792
33.8688
96.0kHz
N/A
N/A
24.5760
36.8640
176.4kHz
22.5792
33.8688
N/A
N/A
192.0kHz
24.5760
36.8640
N/A
N/A
Table 9. System Clock Example (Auto Setting Mode @Serial Mode)
[2] DSD Mode
The external clocks, which are required to operate the AK4397, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4397 is in the normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK4397 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4397 should be reset by PDN pin = “L” after threse clocks are provided. If the
external clocks are not present, the AK4397 should be in the power-down mode (PDN pin = “L”). After exiting
reset(PDN pin = “L”
→
“H”) at power-up etc., the AK4397 is in the power-down mode until MCLK is input.
DCKS bit
MCLK Frequency
0
512fs
1
768fs
Table 10. System Clock (DSD Mode)
Sampling Speed
Normal (fs
≤
32kHz)
Normal
Double
Quad
512fs
16.3840
22.5792
24.5760
N/A
N/A
N/A
N/A
768fs
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
DCLK Frequency
64fs
64fs
(default)
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