參數(shù)資料
型號(hào): AK4394VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: ADVANCED MULTI-BIT 192KHZ 24-BIT DAC
中文描述: 先進(jìn)的多位192kHz的24位DAC
文件頁(yè)數(shù): 19/26頁(yè)
文件大小: 299K
代理商: AK4394VF
ASAHI KASEI
[AK4394]
M0081-E-00
1999/11
- 19 -
n
Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
Notes:
Control 1
Control 2
Test
0
CKS2
DZFM
GA0
CKS1
SLOW
TEST5
CKS0
DFS1
TEST4
DIF2
DFS0
TEST3
DIF1
DEM1
TEST2
DIF0
DEM0
TEST1
RSTN
SMUTE
TEST0
DZFE
GA1
For addresses from 03H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the only internal timing is reset and the registers are not initialized to their default
values.
DIF0-2, CKS1, DFS0 bits are ORed with pins respectively.
n
Register Definitions
Addr
00H
Register Name
Control 1
default
D7
0
0
D6
CKS2
0
D5
CKS1
0
D4
CKS0
0
D3
DIF2
0
D2
DIF1
0
D1
DIF0
0
D0
RSTN
1
RSTN: Internal timing reset
0: Reset. All registers are not initialized.
1: Normal Operation
When the states of CKS2-0 or DFS1-0 change, the AK4394 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (see Table 6)
Initial: “000”, Mode 0
Register bits are ORed with DIF2-0 pins if P/S = “L”.
CKS2-0: Master Clock Frequency Select (see Table 2)
Initial: “000”, Mode 0
CKS1 register bit is ORed with CKS1 pin if P/S = “L”.
Addr
01H
Register Name
Control 2
default
D7
D6
D5
D4
DFS1
0
D3
DFS0
0
D2
D1
D0
DZFE
0
DZFM
0
SLOW
0
DEM1
0
DEM0
0
SMUTE
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis response (see Table 7)
Initial: “00”, 44.1kHz
DFS1-0: Sampling speed control
(see Table 1)
00: Normal speed
01: Double speed
10: Quad speed
Register bit of DFS0 is ORed with DFS0 pin if P/S = “L”.
When changing between Normal/Double Speed Mode and Quad Speed Mode, DFS1 bit should be
changed after changing MCLK frequency. Some click noise occurs at that time.
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