參數(shù)資料
型號: AK4394VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: ADVANCED MULTI-BIT 192KHZ 24-BIT DAC
中文描述: 先進的多位192kHz的24位DAC
文件頁數(shù): 15/26頁
文件大?。?/td> 299K
代理商: AK4394VF
ASAHI KASEI
[AK4394]
M0081-E-00
1999/11
- 15 -
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Zero detection
The AK4394 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for
8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data
of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin of both
channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H”
only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be
disabled by DZFE bit. In this case, DZF pins of both channels are always “L”.
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Soft
mute
operation
Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -
during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually
changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the
operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE
Attenuation
DZF
1024/fs
(1)
0dB
-
AOUT
1024/fs
8192/fs
GD
(2)
GD
(3)
(4)
Notes:
(1) The output signal is attenuated by -
during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft mute and zero detection
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