參數(shù)資料
型號: AK4394VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: ADVANCED MULTI-BIT 192KHZ 24-BIT DAC
中文描述: 先進(jìn)的多位192kHz的24位DAC
文件頁數(shù): 16/26頁
文件大?。?/td> 299K
代理商: AK4394VF
ASAHI KASEI
[AK4394]
M0081-E-00
1999/11
- 16 -
n
System Reset
The AK4394 should be reset once by bringing PDN = “L” upon power-up. The AK4394 is powered up and the internal timing starts
clocking by LRCK “
-
” after exiting reset and power down state by MCLK. The AK4394 is in the power-down mode until MCLK and
LRCK are input.
n
Power-Down
The AK4394 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure 6 shows an
example of the system timing at the power-down and power-up.
Normal Operation
Internal
State
PDN
Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1)
(3)
(6)
DZFL/DZFR
External
MUTE
(5)
(3)
(1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up sequence example
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