
[AK4345]
2.3-wire
μ
P I/F mode (MODE bit = “1”)
Internal registers may be written by 3-wire μP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). AK4345 latches the data on the rising edge of CCLK, so data should clocked in
on the falling edge. The writing of data becomes valid by 16th CCLK after a high to low transition of CSN. CSN should be
set to “H” once after 16 CCLKs for each address. The clock speed of CCLK is 5MHz (max).
PDN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers
are not initialized.
CDTI
CCLK
CSN
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 21. Control I/F Timing
*The AK4345 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4345 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
■
DAC and DIT input select
The AK4345 can select 4-wire
μ
P I/F mode (MODE bit = “0”) or 3-wire
μ
P I/F mode (MODE bit = “1”). In 3-wire
μ
P I/F
mode, the AK4345 can select the input data of DAC and DIT from SDTI1 or SDTI2 data.
MODE
SEL1
SEL0
0
x
x
1
0
0
1
0
1
1
1
0
1
1
1
μ
P I/F
4-wire
3-wire
3-wire
3-wire
Reserved
DAC input
SDTI1
SDTI1
SDTI2
SDTI2
DIT input
SDTI1
SDTI1
SDTI2
Bypass
(x: Don’t care)
Table 6. DAC and DIT Input
MS0635-E-00
2007/06
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