參數(shù)資料
型號(hào): AK4345
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
中文描述: 100dB的96kHz的24位立體聲3.3ツヒDAC,具有動(dòng)態(tài)網(wǎng)
文件頁數(shù): 18/26頁
文件大小: 540K
代理商: AK4345
[AK4345]
μ
P Control Interface
The AK4345 can select 4-wire
μ
P I/F mode (MODE bit = “0”) or 3-wire
μ
P I/F mode (MODE bit = “1”).
1.4-wire
μ
P I/F mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire
μ
P interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “01”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after 16 CCLKs. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
CSN
CCLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
WRITE
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
READ
D4
D5
D6
D7
D0
D1
D2
D3
Hi-Z
C1-C0: Chip Address: (Fixed to “01”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 20. 4-wire Serial Control I/F Timing
*When the AK4345 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
MS0635-E-00
2007/06
- 18 -
相關(guān)PDF資料
PDF描述
AK4345ET 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
AK4346 3.3V 192kHz 24-Bit 6-Channel DAC
AK4346EF 3.3V 192kHz 24-Bit 6-Channel DAC
AK4346VF 3.3V 192kHz 24-Bit 6-Channel DAC
AK4348 3.3V 192kHz 24-Bit 8-Channel DAC
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