參數(shù)資料
型號: AK4345
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
中文描述: 100dB的96kHz的24位立體聲3.3ツヒDAC,具有動態(tài)網(wǎng)
文件頁數(shù): 17/26頁
文件大?。?/td> 540K
代理商: AK4345
[AK4345]
(2) RESET by MCLK stop (PDN pin = “H”)
When MCLK stops, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage.
PDN pin
(1)
Normal Operation
Internal
State
Reset
Normal Operation
GD
GD
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(2)
(3)
External
MUTE
(6)
VCOM
(2)
MCLK Stop
Power-down
Power-down
(4)
(4)
(4)
Hi-Z
(6)
(6)
(5)
Notes:
(1)
PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7
μ
F is attached between VCOM pin and
VSS.
(2)
The analog output corresponding to digital input has the group delay (GD).
(3)
The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section
can be reduced.
(4)
Click noise occurs in 3
4LRCK at both edges (
) of PDN signal, MCLK inputs and MCLK stops. This noise is
output even if “0” data is input.
(5)
The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop).
(6)
Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 19. Reset Sequence Example 2
MS0635-E-00
2007/06
- 17 -
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