參數(shù)資料
型號(hào): AK4345
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
中文描述: 100dB的96kHz的24位立體聲3.3ツヒDAC,具有動(dòng)態(tài)網(wǎng)
文件頁(yè)數(shù): 15/26頁(yè)
文件大?。?/td> 540K
代理商: AK4345
[AK4345]
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15μs) and is controlled by DEM0
and DEM1. In double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
(default)
Table 5. De-emphasis Filter Control (Normal Speed Mode)
Power-down
The AK4345 is placed in the power-down mode by bringing PDN pin = “L”. and the digital filter is reset at the same time.
This reset should always be done after power up.
PDN
Normal Operation
Internal
State
Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(2)
(4)
External
MUTE
(6)
(4)
(2)
Mute ON
(3)
(5)
Don’t care
(1)
Notes:
(1)
PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7
μ
F is attached between VCOM pin and
VSS.
(2)
The analog output corresponding to digital input has the group delay (GD).
(3)
When PDN pin = “L”, the analog output is Hi-Z.
(4)
Click noise occurs in 3
4LRCK at both edges (
) of PDN signal. This noise is output even if “0” data is input.
(5)
The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = “L”).
(6)
Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 17. Power-down/up sequence example
MS0635-E-00
2007/06
- 15 -
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