參數(shù)資料
型號: AK4121A
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Asynchronous Sample Rate Converter
中文描述: 異步采樣率轉(zhuǎn)換器
文件頁數(shù): 9/19頁
文件大?。?/td> 353K
代理商: AK4121A
[AK4121A]
OPERATION OVERVIEW
System Clock
The input port works in slave mode only. The output port works in slave and master mode. An internal system clock is
created by the internal PLL using ILRCK. The MCLK is not needed when the output port is in slave mode, and the
MCLK pin should be connected to DVSS. The CMODE2-0 pins must be controlled when PDN pin =“L”.
Mode
CMODE2
CMODE1
CMODE0
0
L
L
L
256fso (fso~96kHz)
1
L
L
H
384fso (fso~96kHz)
2
L
H
L
512fso (fso~48kHz)
3
L
H
H
768fso (fso~48kHz)
4
H
L
L
Not used. Set to DVSS
5
H
L
H
6
H
H
L
7
H
H
H
Not used. Set to DVSS
Table 1. Master/Slave control
Audio Interface Format
The IDIF2-0 pins select the data mode for the input port. The ODIF1-0 pins select the data mode for the output port. In
all modes the audio data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of OBICK.
Select these modes when PDN pin=“L”. In BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode
IDIF2
IDIF1
IDIF0
0
L
L
L
1
L
L
H
2
L
H
L
20/16bit I
2
S Compatible
3
L
H
H
4
H
L
L
Table 2. Input Audio Data Formats
Mode
ODIF1
ODIF0
SDTO Format
0
L
L
16bit LSB Justified
1
L
H
20bit LSB Justified
2
H
L
20/16bit MSB Justified
20/16bit I
2
S Compatible
3
H
H
Table 3. Output Audio Data Formats
MCLK
Master/Slave (Output Port)
Master
Master
Master
Master
Slave
(Reserved)
(Reserved)
Master (BYPASS mode)
-
-
SDTI Format
16bit LSB Justified
20bit LSB Justified
20bit MSB Justified
IBICK (Slave)
32fs
40fs
40fs
40fs or 32fs
48fs
24bit LSB Justified
OBICK (Slave)
64fs
64fs
40fs or 32fs
40fs or 32fs
OBICK (Master)
64fs
64fs
64fs
64fs
MS0337-E-02
2007/07
- 9 -
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