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參數(shù)資料
| 型號： | AK4121A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Asynchronous Sample Rate Converter |
| 中文描述： | 異步采樣率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 353K |
| 代理商： | AK4121A |
[AK4121A]
■
System Reset
Bringing the PDN pin=“L” places the AK4121A in the power-down mode and initializes the digital filter. This reset
should always be done after power-up. When the PDN pin = “L”, the SDTO output is “L”. Regarding the SDTO valid
time, please refer to the Table 5. Until the output data becomes valid, the SDTO pin outputs “L”.
Case 1
Case 2
External clocks
(output port)
t
a
External clocks
(input port)
SDTI
don’t care
SDTO
(internal state)
Power-down
normal
operation
PLL lock &
fs detection
t
b
normal data
(state1)
External clocks
(output port)
don’t care
don’t care
PDN
Power-down
don’t care
don’t care
don’t care
“0” data
normal
operation
PLL lock &
fs detection
(1)
normal data
PD
(state1)
(state1)
(state2)
(state2)
(state2)
“0” data
“0” data
External clocks
(input port)
SDTI
SDTO
(internal state)
Power-down
normal
operation
PLL lock &
fs detection
(1)
normal data
(no clock)
PDN
Power-down
don’t care
don’t care
don’t care
“0” data
PLL
Unlock
(state1)
(state1)
(state1)
“0” data
(don’t care)
(don’t care)
Note:
(1) <100ms for recommended value 2, <200ms for recommended value 1. (Figure 11)
Figure 9. System Reset
Reset time
t
a
≤
10ms
10ms<
Table 5. Reset time t
a
and Data valid time t
b.
Data valid time
t
b
<100ms
<200ms
MS0337-E-02
2007/07
- 12 -
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| AK4121A_10 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Sample Rate Converter |
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