
[AK4121A]
SWITCHING CHARACTERISTICS
(Ta=
40
~
85
°
C; VDD=3.0~3.6V; TVDD=3.0~5.5V; C
L
=20pF)
Parameter
Master Clock Input (MCLK)
Frequency
Duty Cycle
L/R clock for Input data (ILRCK)
Frequency
Duty Cycle
L/R clock for Output data (OLRCK)
Frequency
Duty Cycle
Audio Interface Timing
Input
IBICK Period
IBICK Pulse Width Low
IBICK Pulse Width High
ILRCK Edge to IBICK “
↑
” (Note 9)
ILRCK period (8KHz ~ 32KHz)
ILRCK period (32KHz ~ 48KHz)
ILRCK period (48KHz ~ 96KHz)
BICK “
↑
” to ILRCK Edge (Note 9)
SDTI Hold Time from IBICK “
↑
”
SDTI Setup Time to IBICK “
↑
”
Output (Slave Mode)
OBICK Period
OBICK Pulse Width Low
OBICK Pulse Width High
OLRCK Edge to OBICK “
↑
” (Note 9)
OBICK “
↑
” to OLRCK Edge (Note 9)
OLRCK to SDTO (MSB)
OBICK “
↓
” to SDTO
Output (Master Mode)
BICK Frequency
BICK Duty
BICK “
↓
” to LRCK
BICK “
↓
” to SDTO
Power-down & Reset Timing
PDN Pulse Width (Note 10)
Note 8. Min is 8kHz when BYPASS=“H”.
Note 9. BICK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK4121A must be reset by bringing PDN pin “H” to “L” upon power-up.
Symbol
fCLK
dCLK
fs
Duty
fs
Duty
Duty
tBCK
tBCKL
tBCKH
tBLR
tBLR
tBLR
tLRB
tSDH
tSDS
tBCK
tBCKL
tBCKH
tBLR
tLRB
tLRS
tBSD
fBCK
dBCK
tMBLR
tBSD
tPD
min
8.192
40
8
48
32
48
1/64fs
65
65
1/256fs+45
1/256fs+25
1/256fs+15
30
30
30
typ
-
-
50
50
50
max
36.864
60
96
52
96
52
Units
MHz
%
kHz
%
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
(Note 8)
Slave Mode
Master Mode
1/64fs
65
65
30
30
20
20
150
30
30
20
30
64fs
50
MS0337-E-02
2007/07
- 6 -