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參數(shù)資料
| 型號(hào)： | AK4121A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Asynchronous Sample Rate Converter |
| 中文描述： | 異步采樣率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 353K |
| 代理商： | AK4121A |
[AK4121A]
■
Internal Reset Function for Clock Change
The AK4121A is reset automatically when the output clock is stopped. If the output clock is started again, normal data
is output within 100ms.
■
Sequence of changing clocks
The recommended sequence for changing clocks is shown in Figure 10.
External clocks
(input port
or output port)
< 10msec
PLL locktime
& fs detection
Power
down
state 1
SDTO
(interlal state)
normal operation
normal operation
state 2
(unknown)
< 100msec
SMUTE
(2)
(recommended)
1024/fso
Att.Level
0dB
-
∞
dB
normal data
normal data
1024/fso
PDN
(1)
Figure 10. Sequence of changing clocks
Note:
(1) The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before the PDN pin
changes to “L”, which will cause the data on SDTO to remain “0”.
(2) SMUTE can also be used to remove the unknown data.
MS0337-E-02
2007/07
- 13 -
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相關(guān)代理商/技術(shù)參數(shù) |
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| AK4121A_10 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Sample Rate Converter |
| AK4121AVF | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Sample Rate Converter |
| AK4122 | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 96kHz SRC with DIR |
| AK4122_1 | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 96kHz SRC with DIR |
| AK4122A | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 96kHz SRC with DIR |
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