參數(shù)資料
型號(hào): AK4121A
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Asynchronous Sample Rate Converter
中文描述: 異步采樣率轉(zhuǎn)換器
文件頁(yè)數(shù): 14/19頁(yè)
文件大?。?/td> 353K
代理商: AK4121A
[AK4121A]
Grounding and Power Supply Decoupling
The AK4121A requires careful attention to power supply and grounding arrangements. VDD are usually supplied from
the system’s analog supply.
AVSS and DVSS of the AK4121A must be connected to the analog ground plane.
System analog ground and digital ground should be connected together as close as possible to where the supplies are
brought onto the printed circuit board. Decoupling capacitors especially a 0.1
μ
F ceramic capacitor for high frequency
noise should be placed as near to VDD as possible.
PLL Loop-Filter
The C1 (4.7
μ
F) and R (560ohms) should be connected in series and attached between FILT pin and AVSS in parallel
with C2 (1.0nF). A Care should be taken to ensure that noise on the FILT pin is minimized.
AK4121A
FILT
C1
R
AVSS
C2
Parameter
R
C1
C2
FSI range
Recommended value 1
560ohm +/
8%
4.7
μ
F +/
40%
1.0nF +/
40%
8k ~ 96kHz
Recommended value 2
1.2kohm +/
8%
2.2
μ
F +/
40%
2.2nF +/
40%
16k ~ 96kHz
Note 13. Those recommended values include temperature dependence.
Figure 11. PLL Loop-Filter
MS0337-E-02
2007/07
- 14 -
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