
ADV7850
Data Sheet
Rev. 0 | Page 10 of 32
TIMING CHARACTERISTICS
Data, SPI, and I2C Timing Characteristics
Table 5.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CLOCK AND CRYSTAL
Crystal Frequency
27
MHz
Crystal Frequency Stability
±50
ppm
SCL Frequency
400
kHz
SCL Minimum Pulse Width High
t1
600
ns
SCL Minimum Pulse Width Low
t2
1.3
μs
Start Condition Hold Time
t3
600
ns
Start Condition Setup Time
t4
600
ns
SDA Setup Time
t5
100
ns
SCL and SDA Rise Time
t6
1000
ns
SCL and SDA Fall Time
t7
300
ns
Stop Condition Setup Time
t8
0.6
μs
RESET FEATURE
Reset Pulse Width
5
ms
HDMI AUDIO I2S PORT, MASTER MODE
HA_SCLK Mark-Space Ratio
t15:t16
45:55
% duty cycle
t17
End of valid data to negative
HA_SCLK edge
2
ns
t18
Negative HA_SCLK edge to start of
valid data
2
ns
t19
End of valid data to negative
HA_SCLK edge
2
ns
t20
Negative HA_SCLK edge to start of
valid data
2
ns
AUDIO CODEC MASTER CLOCK
AC_MCLK Frequency Range
fMCLK
4.096
24.576
MHz
AC_MCLK Frequency
fMCLK
128 × fS
Hz
SPI READ AND WRITE OPERATIO
NS1SCLK Frequency
13.5
MHz
Master Mode
TTX_SCLK Falling Edge to
CS/TTX_MOSI Valid
t21, t22
3.0
4.1
ns
TTX_MISO Setup Time
t23
15.3
ns
TTX_MISO Hold Time
t24
2.1
ns
Slave Mode
CS Falling Edge to TTX_SCLK
Rising Edge
t25, t26
4.0
ns
TTX_SCLK Falling Edge to CS
Rising Edge
t27, t28
4.0
ns
TTX_MOSI Setup Time
t29
1.8
ns
TTX_MOSI Hold Time
t30
2.7
ns
TTX_SCLK Falling Edge to
CS/MOSI Valid
t31, t32
7.3
15.5
ns
1 Guaranteed by design.
2 LRCLK is a signal accessible via HA_AP5.
3 I2Sx are signals accessible via Ball HA_AP1 to Ball HA_AP4.