參數(shù)資料
型號(hào)： ADV7344
廠商： Analog Devices, Inc.
英文描述： Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs
中文描述： 多格式視頻編碼器6 14位噪聲整形視頻DAC
文件頁數(shù)： 75/88頁
文件大?。?/td> 1078K
代理商： ADV7344
ADV7344
APPENDIX 5—SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV7344 is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All
timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. If the S_VSYNC and S_HSYNC pins are not used, they should be tied high during this mode.
Rev. 0 | Page 75 of 88
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
YC
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
0
Figure 100. SD Slave Mode 0
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV7344 generates H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is output on
S_HSYNC and the F bit is output on S_VSYNC.
522
523
524
525
8
9
10
11
20
21
22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
H
F
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
H
F
7
6
5
4
3
2
1
0
Figure 101. SD Master Mode 0, NTSC
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