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參數(shù)資料
| 型號： | ADV7344 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| 中文描述： | 多格式視頻編碼器6 14位噪聲整形視頻DAC |
| 文件頁數(shù)： | 27/88頁 |
| 文件大?。?/td> | 1078K |
| 代理商： | ADV7344 |
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ADV7344
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV7344 via the MPU port, except for registers that are
specified as read-only or write-only registers.
The subaddress register determines which register the next
read or write operation accesses. All communication through
the MPU port starts with an access to the subaddress register.
A read/write operation is then performed from/to the target
address, which increments to the next address until the
transaction is complete.
Rev. 0 | Page 27 of 88
REGISTER PROGRAMMING
Table 14 to Table 28 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines to or
from which register the operation takes place.
Table 14. Register 0x00
SR7 to
SR0
Register
0x00
Power
Mode
Register
Bit Description
Sleep Mode. With this control enabled, the current consumption
is reduced to μA level. All DACs and the internal PLL circuit are
disabled. I
2
C registers can be read from and written to in sleep
mode.
Bit Number
5
4 3 2 1 0
Register
Setting
Sleep
mode off.
Sleep
mode on.
PLL on.
PLL off.
Reset
Value
0x12
7
6
0
1
0
1
PLL and Oversampling Control. This control allows the internal
PLL circuit to be powered down and the oversampling to be
switched off.
DAC 3: Power on/off.
0
1
0
1
0
1
0
1
0
1
0
1
DAC 3 off.
DAC 3 on.
DAC 2 off.
DAC 2 on.
DAC 1 off.
DAC 1 on.
DAC 6 off.
DAC 6 on.
DAC 5 off.
DAC 5 on.
DAC 4 off.
DAC 4 on.
DAC 2: Power on/off.
DAC 1: Power on/off.
DAC 6: Power on/off.
DAC 5: Power on/off.
DAC 4: Power on/off.
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