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參數(shù)資料
| 型號： | ADV7344 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| 中文描述： | 多格式視頻編碼器6 14位噪聲整形視頻DAC |
| 文件頁數(shù)： | 46/88頁 |
| 文件大?。?/td> | 1078K |
| 代理商： | ADV7344 |
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ADV7344
Whether the ED/HD Y data is clocked in upon the rising or
falling edge of CLKIN_B is determined by Subaddress 0x01,
Bits[2:1] (See the input sequence shown in Figure 52 and
Figure 53).
Rev. 0 | Page 46 of 88
CLKIN_A
CLKIN_B
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7344
S_VSYNC,
S_HSYNC
ED
DECODER
27MHz
10
CrCb
CrCb
10
Y
3
2
YCrCb
27MHz
10
SD
DECODER
525p
OR
625p
0
Figure 55. Simultaneous SD and ED Example Application
CLKIN_A
CLKIN_B
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7344
S_VSYNC,
S_HSYNC
HD
DECODER
74.25MHz
10
CrCb
10
Y
3
2
YCrCb
27MHz
10
SD
DECODER
1080i
OR
720p
OR
1035i
0
Figure 56. Simultaneous SD and HD Example Application
ENHANCED DEFINITION ONLY (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the P_HSYNC,
P_VSYNC, and P_BLANK pins.
The interleaved pixel data is input on Pin Y9 to Pin Y2/Y0, with
Y0 being the LSB in 10-bit input mode.
3FF
00
00
XY
Cb0
Y0
Y1
Cr0
CLKIN_A
Y[9:0]
0
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECO
DER
CLKIN_A
Y[9:0]
54MHz
ADV7344
P_VSYNC,
P_HSYNC,
P_BLANK
YCrCb
10
YCrCb
3
INTERLACED TO
PROGRESSIVE
0
Figure 58. ED Only (at 54 MHz) Example Application
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