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參數(shù)資料
| 型號： | ADV7321 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數(shù)： | 69/88頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | ADV7321 |
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ADV7320/ADV7321
APPENDIX 3—SD CLOSED CAPTIONING
[Subaddresses 0x51 to 0x54]
Rev. 0 | Page 69 of 88
The ADV7320/ADV7321 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of the even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by Logic 1 start bit. Sixteen bits of data follow the start
bit. These consist of two 8-bit bytes, seven data bits, and one
odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Addresses 0x53 to 0x54].
The ADV7320/ADV7321 also support the extended closed
captioning operation, which is active during even fields and
encoded on Scan Line 284. The data for this operation is stored
in the SD closed captioning registers [Addresses 0x51 to 0x52].
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the
ADV7320/ ADV7321. All pixels inputs are ignored during
Lines 21 and 284 if closed captioning is enabled.
FCC Code of Federal Regulations (CFR) 47 section 15.119 and
EIA608 describe the closed captioning information for Line 21
and Line 284.
The ADV7320/ADV7321 use a single buffering method. This
means that the closed captioning buffer is only 1 byte deep;
therefore, there will be no frame delay in outputting the closed
captioning data, unlike other 2-byte-deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
VSYNC to interrupt a microprocessor, which in turn will load
the new data (2 bytes) in every field. If no new data is required
for transmission, 0s must be inserted in both data registers; this
is called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21, or a TV will not recognize
them. If there is a message such as “Hello World” that has an
odd number of characters, it is important to add a blank
character at the end so that the end-of-caption, 2-byte control
code lands in the same field.
D0–D6
D0–D6
10.5
±
0.25
μ
s
12.91
μ
s
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F
= 3.579545MHz
AMPLITUDE = 40 IRE
10.003
μ
s
50 IRE
40 IRE
27.382
μ
s
33.764
μ
s
BYTE 1
BYTE 0
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
0
Figure 98. Closed Captioning Waveform, NTSC
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| ADV7321KSTZ | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7321KST | 制造商:Analog Devices 功能描述:VID ENCODER 6DAC 12-BIT 64LQFP - Bulk |
| ADV7321KSTZ | 功能描述:IC VID ENC 6-12BIT DAC'S 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7322 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 11-Bit HDTV Video Encoder |
| ADV73225709 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73225710 | 制造商:LG Corporation 功能描述:Frame Assembly |
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