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參數(shù)資料
| 型號： | ADV7321 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數(shù)： | 42/88頁 |
| 文件大小： | 1002K |
| 代理商： | ADV7321 |
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ADV7320/ADV7321
HD ASYNC TIMING MODE
[Subaddress 0x10, Bits 3 and 2]
Rev. 0 | Page 42 of 88
For any input data that does not conform to the standards
selectable in input mode, Subaddress 0x10, asynchronous
timing mode can be used to interface to the ADV7320/ADV7321.
Timing control signals for HSYNC, VSYNC, and BLANK must
be programmed by the user. Macrovision and programmable
oversampling rates are not available in async timing mode.
In async mode, the PLL must be turned off [Subaddress 0x00,
Bit 1 = 1]. Register 0x10 should be programmed to 0x01.
Figure 58 and Figure 59 show examples of how to program the
ADV7320/ADV7321 to accept a high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R
BT.1358.
Table 26 must be followed when programming the control signals
in async timing mode. For standards that do not require a trisync
level, P_BLANK must be tied low at all times.
Table 26. Async Timing Mode Truth Table
P_HSYNC P_VSYNC P_BLANK
1
1
→
0
0
0
0
→
1
0
→
1
0 or 1
1
0 or 1
1
0 or 1
Reference
50% point of falling edge of trilevel horizontal sync signal
25% point of rising edge of trilevel horizontal sync signal
50% point of falling edge of trilevel horizontal sync signal
50% start of active video
50% end of active video
Reference in Figure 58
and Figure 59
a
b
c
d
e
0 or 1
0 or 1
0
0
→
1
1
→
0
1
When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 0x10, Bit 6.
CLK
ACTIVE VIDEO
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
81
66
66
243
1920
HORIZONTAL SYNC
e
d
c
b
a
SET ADDRESS 0x14,
BIT 3 = 1
0
P_HSYNC
P_VSYNC
P_BLANK
Figure 58. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
ACTIVE VIDEO
0
1
HORIZONTAL SYNC
e
d
c
b
a
CLK
SET ADDRESS 0x14
BIT 3 = 1
ANALOG OUTPUT
0
P_VSYNC
P_BLANK
P_HSYNC
Figure 59. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7321KST | 制造商:Analog Devices 功能描述:VID ENCODER 6DAC 12-BIT 64LQFP - Bulk |
| ADV7321KSTZ | 功能描述:IC VID ENC 6-12BIT DAC'S 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7322 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 11-Bit HDTV Video Encoder |
| ADV73225709 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73225710 | 制造商:LG Corporation 功能描述:Frame Assembly |
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