參數(shù)資料
型號(hào)： ADV7321
廠商： Analog Devices, Inc.
英文描述： Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
中文描述： 多格式視頻編碼器216兆赫六噪聲整形的12位DAC
文件頁(yè)數(shù)： 43/88頁(yè)
文件大?。?/td> 1002K
代理商： ADV7321
ADV7320/ADV7321
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal
and vertical counters remain reset. When this bit is set back to 0,
the internal counters resume counting.
Rev. 0 | Page 43 of 88
The minimum time the pin must be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
SD REAL-TIME CONTROL, SUBCARRIER RESET,
AND TIMING RESET
[Subaddress 0x44, Bits 2 and 1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 0x44, Bits 1 and 2], the ADV7320/ADV7321 can be
used in (a) timing reset mode, (b) subcarrier phase reset mode,
or (c) RTC mode.
a.
A timing reset is achieved in a low-to-high transition
on the RTC_SCR_TR pin (Pin 31). In this state, the
horizontal and vertical counters remain reset. Upon
releasing this pin (set to low), the internal counters
resume counting, starting with Field 1, and the
subcarrier phase is reset.
The minimum time the pin must be held high is one
clock cycle; otherwise, this reset signal might not be
recognized. This timing reset applies to the SD timing
counters only.
b.
In subcarrier phase reset, a low-to-high transition on
the RTC_SCR_TR pin (Pin 31) resets the subcarrier
phase to zero on the field following the subcarrier
phase reset when the SD RTC/TR/SCR control bits at
Address 0x44 are set to 01.
This reset signal must be held high for a minimum of
one clock cycle.
Because the field counter is not reset, it is
recommended that the reset signal is applied in Field 7
(PAL) or Field 3 (NTSC). The reset of the phase will
then occur on the next field, i.e., Field 1, lined up
correctly with the internal counters. The field count
register at Address 0x7B can be used to identify the
number of the active field.
c.
In RTC mode, the ADV7320/ADV7321 can be used to
lock to an external video source. The real-time control
mode allows the ADV7320/ADV7321 to automatically
alter the subcarrier frequency to compensate for line
length variations. When the part is connected to a
device, such as an ADV7183A video decoder (see
Figure 62), that outputs a digital data stream in the
RTC format, the part will automatically change to the
compensated subcarrier frequency on a line-by-line
basis. This digital data stream is 67 bits wide and the
subcarrier is contained in Bits 0 to 21. Each bit is two
clock cycles long. Write 0x00 into all four subcarrier
frequency registers when this mode is used.
DISPLAY
NO TIMING RESET APPLIED
TIMING RESET APPLIED
START OF FIELD 4 OR 8
F
SC
PHASE = FIELD 4 OR 8
F
SC
PHASE = FIELD 1
TIMING RESET PULSE
307
310
307
1
2
3
4
5
6
7
21
313
320
DISPLAY
START OF FIELD 1
0
Figure 60. Timing Reset Timing Diagram
相關(guān)PDF資料
PDF描述
ADV7321KSTZ Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7324 Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
ADV7324KSTZ Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
ADV7340 Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS
ADV7340BSTZ Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7321KST 制造商:Analog Devices 功能描述:VID ENCODER 6DAC 12-BIT 64LQFP - Bulk
ADV7321KSTZ 功能描述:IC VID ENC 6-12BIT DAC'S 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7322 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 11-Bit HDTV Video Encoder
ADV73225709 制造商:LG Corporation 功能描述:Frame Assembly
ADV73225710 制造商:LG Corporation 功能描述:Frame Assembly
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