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參數(shù)資料
| 型號(hào)： | ADV7321 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數(shù)： | 59/88頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | ADV7321 |
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ADV7320/ADV7321
Rev. 0 | Page 59 of 88
FILTER C
FILTER B
FILTER A
FILTER D
FREQUENCY (Hz)
0
0.2
0.4
0.6
M
0.8
1.0
0
0
1
2
3
4
5
6
Figure 81. DNR Input Select
DNR MODE CONTROL
[Address 0x65, Bit 4]
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using Extended SSAF filter).
BLOCK OFFSET CONTROL
[Address 0x65, Bits 7 to 4]
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
SD ACTIVE VIDEO EDGE
[Subaddress 0x42, Bit 7]
When the active video edge feature is enabled, the first three
pixels and the last three pixels of the active video on the luma
channel are scaled so that maximum transitions on these pixels
are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8.
All other active video passes through unprocessed.
SAV/EAV STEP EDGE CONTROL
The ADV7320/ADV7321 have the capability of controlling fast
rising and falling signals at the start and end of active video to
minimize ringing.
An algorithm monitors SAV and EAV and determines when the
edges are rising or falling too fast. The result is reduced ringing
at the start and end of active video for fast transitions.
Subaddress 0x42, Bit 7 = 1, enables this feature.
100 IRE
0 IRE
100 IRE
87.5 IRE
12.5 IRE
0 IRE
50 IRE
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
0
Figure 82. Example of Active Video Edge Functionality
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PDF描述 |
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| ADV7321KSTZ | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| ADV7324 | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| ADV7324KSTZ | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| ADV7340 | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| ADV7340BSTZ | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7321KST | 制造商:Analog Devices 功能描述:VID ENCODER 6DAC 12-BIT 64LQFP - Bulk |
| ADV7321KSTZ | 功能描述:IC VID ENC 6-12BIT DAC'S 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7322 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 11-Bit HDTV Video Encoder |
| ADV73225709 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73225710 | 制造商:LG Corporation 功能描述:Frame Assembly |
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