參數(shù)資料
型號(hào)： ADV7311KST
廠商： Analog Devices Inc
文件頁數(shù)： 41/84頁
文件大?。?/td> 0K
描述： IC VID ENC 6-12BIT DAC'S 64LQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： DVD，SD/HD
電壓 - 電源，模擬： 2.5V
電壓 - 電源，數(shù)字： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（14x14）
包裝： 托盤
REV. A
–46–
ADV7310/ADV7311
SD Hue Adjust Value
[Subaddress 60h]
The hue adjust value is used to adjust the hue on the composite
and chroma outputs.
These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during
the color burst. The ADV7310/ADV7311 provides a range of
22.5
o increments of 0.17578125o. For normal operation (zero
adjustment), this register is set to 80h. FFh and 00h represent the
upper and lower limits (respectively) of adjustment attainable.
(Hue Adjust) [
o] = 0.17578125o
× (HCRd – 128), for positive
hue adjust value.
For example, to adjust the hue by +4
o, write 97h to the Hue
Adjust Value register:
4
0 17578125
128
105
97
.
*
+=
=
dh
*rounded to the nearest integer
To adjust the hue by –4
o, write 69h to the Hue Adjust Value
register:
+=
=
4
0 17578125
128
105
69
.
*
dh
*rounded to the nearest integer
SD Brightness Control
[Subaddress 61h]
The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0IRE to 22.5IRE. For NTSC without pedestal and
PAL, the setup can vary from –7.5IRE to +15IRE.
The brightness control register is an 8-bit register. Seven bits of
this 8-bit register are used to control the brightness level. This
brightness level can be a positive or negative value.
For example:
Standard: NTSC with Pedestal.
To add +20IRE brightness level, write 28h to Address 61h,
SD brightness.
SD BrightnessValue
IREValue
h
hh
[] =
×
[] =
×
[] = [] =
2.015631
20
2.015631
40.31262
28
Standard: PAL.
To add –7IRE brightness level, write 72h to Address 61h,
SD brightness.
IREValue
b
into twos complement
b
h
×
[] =
×
[] = [] =
[]
=
[] =
2.015631
7
2.015631
14.109417
0001110
1110010
72
Table X. Brightness Control Values
*
Setup
Level In
Setup
NTSC with
NTSC No
Level In
SD
Pedestal
PAL
Brightness
22.5 IRE
15 IRE
1Eh
15 IRE
7.5 IRE
0Fh
7.5 IRE
0 IRE
00h
0 IRE
–7.5 IRE
71h
*Values in the range from 3Fh to 44h might result in an invalid output signal.
SD Brightness Detect
[Subaddress 7Ah]
The ADV7310/ADV7311 allow monitoring of the brightness
level of the incoming video data. Brightness detect is a read-only
register.
Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]
Double buffered registers are updated once per field on the
falling edge of the
VSYNC signal. Double buffering improves
the overall performance since modifications to register settings
will not be made during active video, but take effect on the start
of the active video.
Double buffering can be activated on the following HD registers:
HD Gamma A and Gamma B curves and HD CGMS registers.
Double buffering can be activated on the following SD registers:
SD Gamma A and Gamma B curves, SD Y Scale, SD U Scale,
SD V Scale, SD Brightness, SD Closed Captioning, and
SD Macrovision Bits 5–0.
NTSC WITHOUT PEDESTAL
NO SETUP
VALUE ADDED
POSITIVE SETUP
VALUE ADDED
100 IRE
0 IRE
NEGATIVE SETUP
VALUE ADDED
–7.5 IRE
+7.5 IRE
Figure 39. Examples of Brightness Control Values
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