參數(shù)資料
型號(hào)： ADV7311KST
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/84頁(yè)
文件大?。?/td> 0K
描述： IC VID ENC 6-12BIT DAC'S 64LQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 視頻編碼器
應(yīng)用： DVD，SD/HD
電壓 - 電源，模擬： 2.5V
電壓 - 電源，數(shù)字： 2.5V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（14x14）
包裝： 托盤(pán)
REV. A
–38–
ADV7310/ADV7311
Vertical Blanking Interval
The ADV7310/ADV7311 accept input data that contains VBI
data [CGMS, WSS, VITS, and so on] in SD and HD modes.
For SMPTE 293M [525p] standards, VBI data can be inserted
on Lines 13 to 42 of each frame, or on Lines 6 to 43 for the
ITU-R BT.1358 [625p] standard.
For SD NTSC this data can be present on Lines 10 to 20, and
in PAL on Lines 7 to 22.
If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.
In Slave Mode 0, if VBI is enabled, the blanking bit in the
EAV/SAV code is overwritten, and it is possible to use VBI in
this timing mode as well.
In Slave Mode 1 or 2, the
BLANK control bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7310/ADV7311. Otherwise, the ADV7310/ADV7311
automatically blanks the VBI to standard.
If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.
Subcarrier Frequency Registers
[Subaddress 4Ch–4Fh]
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the equation
Subcarrier Frequency Register
Number of subcarrier frequency values in one video line
Number of 27 MHz clk cycles in one video line
=
2
23*
*Rounded to the nearest integer
For example, in NTSC mode,
Subcarrier FrequencyValue
=
×=
227.5
1716
2
569408542
23
Subcarrier Register Value = 21F07C1Eh
SD FSC Register 0: 1Eh
SD FSC Register 1: 7Ch
SD FSC Register 2: F0h
SD FSC Register 3: 21h
Refer to the MPU Port Description section for more details on
how to access the subcarrier frequency registers.
Square Pixel Timing
[Register 42h, Bit 4]
In square pixel mode, the following timing diagrams apply.
Y
C
r
Y
F
0
X
Y
8
0
1
0
8
0
1
0
F
0
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
0
X
Y
C
b
Y C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
Figure 34. EAV/SAV Embedded Timing
FIELD
PIXEL
DATA
PAL = 44 CLOCK CYCLES
NTSC = 44 CLOCK CYCLES
PAL = 136 CLOCK CYCLES
NTSC = 208 CLOCK CYCLES
Cb
Y
Cr
Y
HSYNC
BLANK
Figure 35. Active Pixel Timing
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