參數資料
| 型號： | ADV7202KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC VIDEO 10BIT 64LQFP |
| 產品變化通告： | ADV7xxx Obsolescence 16/Jan/2012 |
| 標準包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數據接口： | 串行 |
| 分辨率（位）： | 12，10 b |
| ADC / DAC 數量： | 1 / 4 |
| 三角積分調變： | 無 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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REV. 0
ADV7202
–11–
VIDEO CLAMPING AND AGC CONTROL
When analog signal clamping is required, the input signal should
be ac-coupled to the input via a capacitor, the clamping control is
via the MPU port. The AGC is implemented digitally. For cor-
rect operation, the user must program the clamp value to which
the signal has been clamped into the ADV7202 I
2C Register.
This allows the user to specify which signal level is unaffected by
the AGC. The digital output signal will be a function of the ADC
output, the AGC Gain, and the Clamp Level and can be repre-
sented as follows:
D
AGC Gain
ADC DATA
Clamp Level
OUT =
×
[]
+
_–
(1)
DOUT will be a 10-bit number (0–1023), the AGC Gain defaults
to 2 and can have a value between 0 to 7.99. The Clamp Level is a
10-bit number (0–1023) equal to the 7-bit I
2C value
16
(Clamp Level CR06-CR00); the ADC value can be regarded as
a 10-bit number (0–1023) for the equation. It should be noted
that the ADC resolution is 12 bits. The above equation is used
to give a basic perspective and is mathematically correct.
When the clamps are operational, Equation 1 shows how the
ADV7202 ensures that the level to which the user is clamping is
unaffected by the AGC loop. When no clamps are operational,
the operation should be regarded as a straightforward gain-and-
level shift.
Equation 1 maps the ADC input voltage range to its output.
AGC Gain
The AGC gain can be set to a value from 0 to 7.99. The AGC
Gain Register holds a 12-bit number that corresponds to the
required gain. The first three MSBs hold the gain integer value
while the remaining nine bits hold the gain fractional value. The
new AGC multiplier is latched when the MSB register is written
to. Example: The user requires a gain of 3.65.
The first three bits give the integer value 3, hence these will be
set to ‘011.’ The remaining nine bits will have to be set to give
the fractional value 0.65, 512
0.65 = 333 = ‘101001101.’ From
Equation 2 it can be seen that the Clamp Level is subtracted from
the signal before AGC is applied and then added on again after-
wards; hence, if the AGC Gain is set to a value of one, the result
would be as follows:
(AGC Gain = 1)
D
ADC DATA
Clamp Level
ADC Data
OUT =+
=
_–
_
(2)
FUNCTIONAL DESCRIPTION
Clamp and AGC Control
The ADV7202 has a front end 3-channel clamp control. To perform
an accurate AGC gain operation, it is necessary to know to what
level the user is clamping the black level; this value is program-
mable in Clamp Register 0 CR00–CR06. Each channel has a fine
and coarse clamp; the clamp direction and its duration are pro-
grammable. Synchronization of the clamps and AGC to the input
signal is possible using the SYNC_IN control pin and setting mode
Register CR14 to Logic Level “1.” Using this method, it is possible
to ensure that AGC and clamping are only applied outside the
active video area.
Control Signals
The function and operation of the SYNC_IN signal is described in
the Clamp and AGC Control section. The SYNC_OUT will go
high while Cr data from a YCrCb data stream or C data from a Y/C
data stream has been output on DOUT[9:0] (see Figures 1 to 3).
I
2C Filter
A selectable internal I
2C filter allows significant noise reduction
on the I2C interface. In setting ALSB high, the input bandwidth
on the I
2C lines is reduced and pulses of less than 50 ns are not
passed to the I
2C controller. Setting ALSB low allows greater
input bandwidth on the I2C lines.
XTAL0
CVBS
DOUT [9:0]
SYNC_OUT
CVBS
Figure 1. SYNC_OUT Output Timing, CVBS Input
XTAL0
DOUT [9:0]
SYNC_OUT
YC
Y
CY
Figure 2. SYNC_OUT Output Timing, Y/C (S-VIDEO) Input
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