參數(shù)資料
型號: ADV7202KSTZ
廠商: Analog Devices Inc
文件頁數(shù): 28/28頁
文件大?。?/td> 0K
描述: IC CODEC VIDEO 10BIT 64LQFP
產(chǎn)品變化通告: ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 12,10 b
ADC / DAC 數(shù)量: 1 / 4
三角積分調(diào)變:
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
REV. 0
ADV7202
–9–
PIN FUNCTION DESCRIPTIONS
Input/
Pin No.
Mnemonic
Output
Function
1
SYNC_IN
I
This signal can be used to synchronize the updating of clamps. Polarity is pro-
grammable via I
2C.
2
SCL
I
MPU Port Serial Interface Clock Input
3
ALSB
I
This signal sets up the LSB of the MPU address. MPU address = 2cH, ALSB = 0,
MPU address = 2eH, ALSB = 1. When this pin is tied high, the I
2C filter is activated,
which reduces noise on the I
2C interface. When this pin is tied low, the input
bandwidth on the I2C lines is increased.
4
XTAL0
I
Input terminal for crystal oscillator or connection for external oscillator with
CMOS-compatible square wave clock signal.
5
XTAL1
O
Second Terminal for Crystal Oscillator. Not connected if external clock source
is used.
6
AVDD_ADC
P
ADC Supply Voltage (5 V or 3.3 V)
7
AVSS_ADC
G
Ground for ADC Supply
8–19
AIN1–AIN6
I
Analog Signal Inputs. Can be configured differentially or single-ended.
20
DVSS
G
Ground for Digital Core Supply
21
REFADC
I/O
Voltage Reference Input or Programmable Reference Out.
22
CML
O
Common-Mode Level for ADCs. Connect a 0.1
F capacitor from CML pin to
AVSS_ADC.
23, 24
CAP2, CAP1
I
ADC Capacitor Network. Connect a 0.1
F capacitor from each CAP pin to
AVSS_ADC and a 10
F capacitor across the two CAP pins.
25
OSDEN
I
Enable data from OSDIN0–OSDIN2 to be switched to the outputs when set to a logic
high.
26–35
DOUT[9:0]
O
ADC Data Output
36
OSDIN2
I
Third Input Channel for On-Screen Display
37
OSDIN1
I
Second Input Channel for On-Screen Display
38
OSDIN0
I
First Input Channel for On-Screen Display
39
DAC3_OUT
O
General-Purpose Analog Output
40
DAC2_OUT
O
Analog Output. Can be used to output CVBS, R, or U.
41
AVSS_DAC
G
Ground for DAC Supply
42
AVDD_DAC
P
DAC Supply Voltage (5 V or 3.3 V)
43
DAC1_OUT
O
Analog Output. Can be used to output CVBS, Y, G, or Luma.
44
DAC0_OUT
O
Analog Output. Can be used to output CVBS, V, B, or Chroma.
45
COMP
O
Compensation pin for DACs. Connect 0.1
F capacitor from COMP pin to
AVDD_DAC.
46
VREFDAC
I/O
DAC Voltage Reference Output Pin, Nominally 1.235 V. Can be driven by an
external voltage reference.
47
RSET
I
Used to control the amplitude of the DAC output current, 1200
resistor gives an
I max of 4.33 mA.
48
RESET
IMaster Reset (Asynchronous)
49–52, 55, 56,
DAC_DATA[9:0]
I
DAC Input Data for Four Video Rate DACs
59–62
53
DVSS
G
Ground for Digital Core Supply
54
DVDD
P
Supply Voltage for Digital Core (5 V or 3.3 V)
57, 58
DACCLK[1:0]
I
DAC Clocks
63
SYNC_OUT
O
Output Sync Signal, which goes to a high state while Cr data sample from a
YCrCb data stream or C data from a Y/C data stream is output on DOUT[9:0].
64
SDA
I/O
MPU Port Serial Data Input/Output
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