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參數(shù)資料
| 型號： | ADV7202KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC VIDEO 10BIT 64LQFP |
| 產(chǎn)品變化通告： | ADV7xxx Obsolescence 16/Jan/2012 |
| 標準包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 12，10 b |
| ADC / DAC 數(shù)量： | 1 / 4 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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REV. 0
ADV7202
–16–
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 16 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
ADC Reference Voltage (MR00)
This control bit is used to select the ADC reference voltage. When
this bit is set to “0,” a reference voltage of 1.1 V is selected. When
the bit is set to “1,” a reference voltage of 2.2 V is selected.
External Reference Enable (MR01)
Setting this bit to “1” enables an external voltage reference for
the ADC.
Voltage Reference Power-Down (MR02)
Setting this bit to “1” causes the internal DAC voltage reference to
power down.
ADC Power-Down (MR03)
Setting this bit to “1” causes the video rate ADC to power down.
Power-Down (MR04)
Setting this bit to “1” puts the device into power-down mode.
Reserved (MR05–MR07)
Zero must be written to these bits.
MR01
MR07
MR02
MR04
MR06
MR03
MR00
MR04
0
NORMAL
1POWER-DOWN
POWER-DOWN
MR02
0
NORMAL
1POWER-DOWN
VREF
POWER-DOWN
MR00
0
1.1V
1
2.2V
ADC REF
VOLTAGE
MR03
0
NORMAL
1POWER-DOWN
ADC
POWER-DOWN
MR01
0
INTERNAL
1
EXTERNAL
EXT REF
ENABLE
MR05
ZERO MUST BE
WRITTEN TO
THESE BITS
MR07–MR05
Figure 16. Mode Register 0
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 17 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC0 Control (MR10)
Setting this bit to “0” enables DAC0; otherwise, this DAC is
powered down.
DAC1 Control (MR11)
Setting this bit to “0” enables DAC1; otherwise, this DAC is
powered down.
DAC2 Control (MR12)
Setting this bit to “0” enables DAC2; otherwise, this DAC is
powered down.
DAC3 Control (MR13)
Setting this bit to “0” enables DAC3; otherwise, this DAC is
powered down.
Dual Edge Clock (MR14)
Setting this bit to “1” allows data to be read into the DACs on
both edges of the clock; hence, data may be read in at twice the
clock frequency. See Figure 17. If this bit is set to “0,” the data
will only be strobed on the rising edge of the clock.
Dual Clock (MR15)
Setting this bit to “1” allows the use of two clocks to strobe data
into the DACs. See Figure 17. It is possible to clock data in
with only one clock and use the second clock to contain timing
information.
4:2:2 Mode (MR16)
Setting this bit to “1” enables data to be input in 4:2:2 format.
4:2:2 mode will only work if MR14 and MR15 register bits are
set to zero.
DAC Input Invert (MR17)
Setting this bit to “1” causes the input data to the DACs to be
inverted allowing for an external inverting amplifier.
MR17
MR12
MR14
MR16
MR14
0SINGLE EDGE
1DUAL EDGE
DUAL EDGE CLOCK
MR15
MR16
0
DISABLE
1ENABLE
4:2:2 MODE
MR15
0SINGLE CLK
1DUAL CLK
DUAL CLOCK
MR13
MR11
MR10
MR13
0
NORMAL
1POWER-DOWN
DAC3 CONTROL
MR17
0
DISABLE
1ENABLE
DAC I/P INVERT
MR12
0
NORMAL
1POWER-DOWN
DAC2 CONTROL
MR10
0
NORMAL
1POWER-DOWN
DAC0 CONTROL
MR11
0
NORMAL
1POWER-DOWN
DAC1 CONTROL
Figure 17. Mode Register 1
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| ADV7280ABCPZ-M | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻 數(shù)據(jù)接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數(shù):1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
| ADV7280ABCPZ-M-RL | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:5,000 |
| ADV7280AWBCPZ | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻 數(shù)據(jù)接口:I2C 分辨率（位）:10 b ADC/DAC 數(shù):1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
| ADV7280AWBCPZ-M | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻 數(shù)據(jù)接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數(shù):1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
| ADV7280AWBCPZ-M-RL | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:視頻 數(shù)據(jù)接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數(shù):1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:5,000 |
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