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參數(shù)資料
| 型號： | ADV7195 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| 中文描述： | 多格式逐行掃描/高清晰度電視編碼器三種11位DAC和10位數(shù)據(jù)輸入 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大?。?/td> | 499K |
| 代理商： | ADV7195 |
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REV. 0
ADV7195
–27–
Test Pattern Hatch/Frame (MR13)
If this bit is set to “0,” a cross-hatch test pattern is output from
the ADV7195. The cross-hatch test pattern can be used to test
monitor convergence.
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7195.
The color of the lines or the frame/field is by default white but
can be programmed to be any color using the Color Y, Color
Cr, Color Cb registers.
VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion
during the Vertical Blanking Interval.
For this purpose Lines 7–20 in 1080i and Lines 6–25 in 720p
can be used for VBI data insertion.
Reserved (MR15–MR17)
A “0” must be written to these bits.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
INPUT
STANDARD
MR05
0
1
1080I
720P
INPUT CONTROL SIGNALS
0
0
1
1
0
1
0
1
HSYNC
/
VSYNC
/DV
EAV/SAV
TSYNC/
SYNC
/DV
RESERVED
MR03
DV POLARITY
0
1
ACTIVE HIGH
ACTIVE LOW
MR06
MR07
ZERO MUST
BE WRITTEN
TO THIS BIT
MR04
ZERO MUST
BE WRITTEN
TO THIS BIT
MR02
OUTPUT STANDARD SELECTION
0
0
1
1
0
1
0
1
EIA770.3
RESERVED
FULL I/P RANGE
RESERVED
MR01 MR00
Figure 50. Mode Register 0
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
TEST PATTERN
HATCH/FRAME
0
1
HATCH
FIELD/FRAME
MR13
VBI OPEN
MR14
0
1
DISABLE
ENABLE
TEST PATTERN
ENABLE
0
1
DISABLE
ENABLE
MR12
PIXEL DATA
ENABLE
0
1
DISABLE
ENABLE
MR10
INPUT FORMAT
0
1
4:4:4 Y CR CB
4:2:2 Y CR CB
MR11
MR17
–
MR15
ZERO MUST
BE WRITTEN
TO THIS BIT
Figure 51. Mode Register 1
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4-SR0) = 01H)
Figure 51 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
When this bit is set to “0,” the pixel data input to the ADV7195
is blanked such that a black screen is output from the DACs.
When this bit is set to “1,” pixel data is accepted at the input
pins and the ADV7195 outputs to the standard set in “Output
Standard Selection” (MR01–00). This bit also must be set to
“1” to enable output of the test pattern signals.
Input Format (MR11)
It is possible to input data in 4:2:2 format or in 4:4:4
HDTV format.
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7195KST | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7196 | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196A | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196AKS | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7197 | Multiformat HDTV Encoder with Three 11-Bit DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
| ADV7196 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
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