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參數(shù)資料
| 型號： | ADV7195 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| 中文描述： | 多格式逐行掃描/高清晰度電視編碼器三種11位DAC和10位數(shù)據(jù)輸入 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 499K |
| 代理商： | ADV7195 |
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REV. 0
ADV7195
–11–
PROGRAMMABLE ADAPTIVE FILTER CONTROL
If the Adaptive Filter Mode is enabled (Progressive Scan mode
only), it is possible to compensate for large edge transitions on
the incoming Y data. Sensitivity and attenuation are all pro-
grammable over the I
2
C. For further information refer to
Sharpness Filter Control and Adaptive Filter Control section.
INPUT/OUTPUT CONFIGURATION
Table I shows possible input/output configurations when using
the ADV7195.
Table I.
Input Format
Output
YCrCb Progressive Scan
4:2:2
4:4:4
YCrCb HDTV
4:2:2
4:4:4
RGB Progressive Scan
4:4:4
RGB HDTV
4:4:4
Async Timing Mode
All Inputs
2
×
1
×
or 2
×
1
×
1
×
2
×
1
×
1
×
10
0
–
80
–
40
–
50
–
60
–
70
–
20
–
30
–
10
5
10
15
20
25
0
30
Figure 8. 2
×
Interpolation Filter 4-Channel
10
0
–
80
–
40
–
50
–
60
–
70
–
20
–
30
–
10
5
10
15
20
25
0
30
Figure 9. Interpolation Filter–CrCb Channels/Cr 4:2:2
Input Data
10
0
–
80
–
40
–
50
–
60
–
70
–
20
–
30
–
10
5
10
15
20
25
0
30
Figure 10. Interpolation Filter–CrCb Channels/Cr 4:4:4
Input Data
MPU PORT DESCRIPTION
The ADV7195 support a 2-wire serial (I
2
C-compatible) micro-
processor bus driving multiple peripherals. Two inputs, Serial
Data (SDA) and Serial Clock (SCL), carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7195 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 11. The
LSB sets either a read or write operation. Logic Level “1” corre-
sponds to a read operation while Logic Level “0” corresponds to
a write operation. A1 is set by setting the ALSB pin of the
ADV7195 to Logic Level “0” or Logic Level “1.” When ALSB is
set to “0,” there is greater input bandwidth on the I
2
C lines,
which allows high-speed data transfers on this bus. When ALSB
is set to “1,” there is reduced input bandwidth on the I
2
C
lines, which means that pulses of less than 50 ns will not pass
into the I
2
C internal controller. This mode is recommended
for noisy systems.
1
X
1
0
1
0
1
A1
ADDRESS
CONTROL
SETUP BY
ALSB
READ/
WRITE
CONTROL
0
1
WRITE
READ
Figure 11. Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transi-
tion on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/
W
bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the Start condition and the correct transmitted
address. The R/
W
bit determines the direction of the data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
| ADV7196 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
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