參數(shù)資料
型號(hào)： ADV7194KST
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
中文描述： COLOR SIGNAL ENCODER, PQFP80
封裝： LQFP-80
文件頁(yè)數(shù)： 35/69頁(yè)
文件大小： 647K
代理商： ADV7194KST
ADV7194
–35–
REV. 0
MODE REGISTER 8
MR8 (MR87–MR80)
(Address (SR4–SR0) = 08H)
Mode Register 8 is an 8-bit-wide register. Figure 63 shows the
various operations under the control of Mode Register 8.
MR8 BIT DESCRIPTION
Progressive Scan Control (MR80)
This control enables the progressive scan inputs, Y0–Y9
,
Cr0–Cr9
,
Cb0–Cb9. To enable this control MR80 has to be set to 1. It
is assumed that the incoming Y
data contains all necessary sync
information.
Note: Simultaneous progressive scan input and 16-bit pixel input
is not possible.
10-Bit Pixel Port (MR84)
This bit selects 8-bit or 10-bit input format. In 8-bit mode, the
LSB of the pixel data is input on Pin 3, in 10-bit mode, on Pin 1.
Double Buffer Control (MR82)
Double Buffering can be enabled or disabled on the Contrast
Control Register, U Scale Register, V Scale Register, Hue Adjust
Control, Closed Captioning Register, Brightness Control Regis-
ter, Gamma Curve Select Bit. Double Buffering is not available in
Mastering Timing mode.
20-, 16-Bit Pixel Port (MR83)
This bit controls whether the ADV7194 is operated in 16-bit
mode (10-Bit Pixel Port disabled, MR 84 = 0, MR83 = 1) or
20-bit mode (10-Bit Pixel Port enabled, MR84 =1, MR83 = 1).
10-Bit Pixel Port (MR84)
This bit selects 8-bit or 10-bit format. In 8-bit mode, the LSB of
the pixel data is input on Pin 3, in 10-bit mode on Pin 1.
DNR Enable Control (MR85)
To enable the DNR process this bit has to be set to 1. If this bit
is set to 0, the DNR processing is bypassed. For further infor-
mation on DNR controls see the DNR Bit Description section.
Gamma Enable Control (MR86)
To enable the programmable gamma correction this bit has
to be set to enabled (MR86 = 1). For further information on
Gamma Correction controls see the Gamma Correction Regis-
ters section.
Gamma Curve Select Control (MR87)
This bit selects which of the two programmable gamma curves is
to be used. When setting MR87 to 0, the gamma correction curve
selected is Curve A. Otherwise, Curve B is selected. Each curve
will have to be programmed by the user. For further information
on Gamma Correction controls see DNR Bit Description and
Gamma Correction sections.
MODE REGISTER 9
MR9 (MR97–MR90)
(Address (SR4–SR0) = 09H)
Mode Register 9 is an 8-bit-wide register. Figure 65 shows the
various operations under the control of Mode Register 9.
MR9 BIT DESCRIPTION
Undershoot Limiter (MR90–MR91)
This control ensures that no luma video data will go below a
programmable level. This prevents any synchronization problems
due to luma signals going below the blanking level. Available
limit levels are –1.5 IRE, –6 IRE, –11 IRE. Note that this facil-
ity is only available in 4
×
Oversampling mode (MR16 = 1). When
the device is operated in 2
×
Oversampling mode (MR16 = 0),
or RGB output without RGB sync is selected, the minimum
luma level is set in Timing Register 0, TR06 (Min Luma Control).
Black Burst Y-DAC (MR92)
It is possible to output a Black Burst signal from the DAC which is
selected to be the Luma DAC (MR22, MR21, MR20). When
this control is set to enabled, MR92 is set to 1. This signal can be
useful for locking two video sources together using professional
video equipment. See also the Black Burst Output section.
Black Burst Luma-DAC (MR93)
It is possible to output a Black Burst signal from the DAC which
is selected to be the Y-DAC (MR22, MR21, MR20). When this
control is set to enabled, MR93 set to 1. This signal can be
useful for locking two video sources together using professional
video equipment. See also the Black Burst Output section.
20 IRE
0 IRE
–
20 IRE
–
40 IRE
21.5 IRE
0 IRE
–
21.5 IRE
–
43 IRE
3.58MHz
COLOR BURST
(9 CYCLES)
4.43MHz
COLOR BURST
(10 CYCLES)
NTSC BLACK BURST SIGNAL
PAL BLACK BURST SIGNAL
Figure 64. Black Burst Signals for PAL and NTSC Standards
Chroma Delay Control (MR95–MR97)
The Chroma signal can be delayed by up to eight clock cycles
at 27 MHz using MR94–95. For further information see also
the Chroma/Luma Delay section.
MR87
MR86
MR85
MR84
MR83
MR82
MR81
MR80
MR83
0
1
20-/16-BIT PIXEL
PORT CONTROL
DISABLE
ENABLE
DNR ENABLE
CONTROL
MR85
0
DISABLE
1
ENABLE
0
1
DISABLE
ENABLE
MR82
DOUBLE BUFFER
CONTROL
0
1
DISABLE
ENABLE
MR86
GAMMA ENABLE
CONTROL
0
1
CURVE A
CURVE B
MR87
GAMMA CURVE
SELECT CONTROL
ZERO MUST
BE WRITTEN
TO THIS BIT
MR81
0
1
DISABLE
ENABLE
MR80
PROGRESSIVE
SCAN CONTROL
MR84
0
1
10-BIT PIXEL
PORT CONTROL
DISABLE
ENABLE
Figure 63. Mode Register 8, MR8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7194KSTZ 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類(lèi)型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱(chēng):Q4645799
ADV7194KSTZ 制造商:Analog Devices 功能描述:TV / Video IC
ADV7195 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
ADV7195KS 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk
ADV7195KST 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
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