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| 型號： | ADV7194KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP80 |
| 封裝： | LQFP-80 |
| 文件頁數(shù)： | 31/69頁 |
| 文件大?。?/td> | 647K |
| 代理商： | ADV7194KST |
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ADV7194
–31–
REV. 0
MODE REGISTER 2
MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 57 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION
RGB/YUV Control (MR20)
This bit enables the output from the DACs to be set to YUV or
RGB output video standard.
DAC Output Control (MR21)
This bit controls the output from DACs A, B, and C. When this
bit is set to 1, Composite, Luma and Chroma Signals are output
from DACs A, B and C (respectively). When this bit is set to 0,
RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC out-
put configurations is shown below.
Pedestal Control (MR23)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid when the device
is configured in PAL mode.
Square Pixel Control (MR24)
This bit is used to setup square pixel mode. This is available in
Slave Mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied. Square
pixel operation is not available in 4
×
Oversampling mode.
Standard I
2
C Control (MR25)
This bit controls the video standard used by the ADV7194.
When this bit is set to 1 the video standard is as programmed in
Mode Register 0 (Output Video Standard Selection). When it is
set to 0, the ADV7194 is forced into the standard selected by
the NTSC_PAL pin. When NTSC_PAL is low the standard is
NTSC, when the NTSC_PAL pin is high, the standard is PAL.
Pixel Data Valid Control (MR26)
After resetting the device this bit has the value 0 and the pixel
data input to the encoder is blanked such that a black screen is
output from the DACs. The ADV7194 will be set to Master
Mode timing. When this bit is set to 1 by the user (via the I
2
C),
pixel data passes to the pins and the encoder reverts to the tim-
ing mode defined by Timing Mode Register 0.
Sleep Mode Control (MR27)
When this bit is set (1), Sleep Mode is enabled. With this mode
enabled the ADV7194 current consumption is reduced to typically
less than 0.1 mA. The I
2
C registers can be written to and read
from when the ADV7194 is in Sleep Mode.
When the device is in Sleep Mode and 0 is written to MR27, the
ADV7194 will come out of Sleep Mode and resume normal
operation. Also, if a
RESET
is applied during Sleep Mode the
ADV7194 will come out of Sleep Mode and resume normal
operation.
For this to operate, Power up in Sleep Mode control has to be
enabled (MR60 is set to a Logic 1), otherwise Sleep Mode is
controlled by the PAL_NTSC and SCRESET/RTC/TR pins.
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
RGB/YUV
CONTROL
MR20
0
1
RGB OUTPUT
YUV OUTPUT
SCART ENABLE
CONTROL
MR22
0
1
DISABLE
ENABLE
SQUARE PIXEL
CONTROL
MR24
0
1
DISABLE
ENABLE
PIXEL DATA
VALID CONTROL
MR26
0
1
DISABLE
ENABLE
DAC OUTPUT
CONTROL
0
1
RGB/YUV/COMP
COMP/LUMA/CHROMA
MR21
PEDESTAL
CONTROL
0
1
PEDESTAL OFF
PEDESTAL ON
MR23
STANDARD I
2
C
CONTROL
MR25
0
1
DISABLE
ENABLE
SLEEP MODE
CONTROL
MR27
0
1
DISABLE
ENABLE
Figure 57. Mode Register 2, MR2
Table V. DAC Output Configuration
MR22
MR21
MR20
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
G (Y)
Y (Y)
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
B (Pb)
U (Pb)
LUMA
LUMA
B (Pb)
U (Pb)
LUMA
LUMA
R (Pr)
V (Pr)
CHROMA
CHROMA
R (Pr)
V (Pr)
CHROMA
CHROMA
CVBS
CVBS
G (Y)
Y (Y)
G (Y)
Y (Y)
G (Y)
Y (Y)
LUMA
LUMA
B (Pb)
U (Pb)
LUMA
LUMA
B (Pb)
U (Pb)
CHROMA
CHROMA
R (Pr)
V (Pr)
CHROMA
CHROMA
R (Pr)
V (Pr)
NOTE
In Progressive Scan Mode (MR80, 1) the DAC output configuration is stated in the brackets.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7194KSTZ | 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
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