參數(shù)資料
型號(hào)： ADV7194KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
中文描述： COLOR SIGNAL ENCODER, PQFP80
封裝： LQFP-80
文件頁數(shù)： 34/69頁
文件大?。?/td> 647K
代理商： ADV7194KST
ADV7194
–34–
REV. 0
MODE REGISTER 6
MR6 (MR67–MR60)
(ADDRESS (SR4–SR0) = 06H)
Mode Register 6 is an 8-bit-wide register. Figure 61 shows the
various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION
Power-Up Sleep Mode Control (MR60)
After
RESET
is applied this control is enabled (MR60 = 0) if
both SCRESET/RTC/TR and NTSC_PAL pins are tied high.
The ADV7194 will then power up in Sleep Mode to facilitate
low power consumption before the I
2
C is initialized. When
this control is disabled (MR60 = 1, via the I
2
C) Sleep Mode con-
trol passes to Sleep Mode Control, MR27.
PPL Enable Control (MR61)
The PLL control should be enabled (MR61 = 0 ) when 4
×
Oversampling is enabled (MR16 = 1). It is also used to reset the
PLL when this bit is toggled.
Reserved (MR62, MR63, MR64)
A Logic 0 must be written to these bits.
Field Counter (MR65, MR66, MR67)
These three bits are read-only bits. The field count can be read
back over the I
2
C interface. In NTSC mode the field count goes
from 0–3, in PAL Mode from 0–7.
MODE REGISTER 7
MR7 (MR77–MR70)
(Address (SR4–SR0) = 07H)
Mode Register 7 is an 8-bit-wide register. Figure 62 shows the
various operations under the control of Mode Register 7.
MR7 BIT DESCRIPTION
Color Control Enable (MR70)
This bit is used to enable control of contrast and saturation of
color. If this bit is set (1) color controls are enabled (Contrast
Control, U-Scale, V-Scale Registers). If this bit is set (0), the color
control features are disabled.
Luma Saturation Control (MR71)
When this bit is set (1), the luma signal will be clipped if it reaches
a limit that corresponds to an input luma value of 255 (after
scaling by the Contrast Control Register). This prevents the
chrominance component of the composite video signal being
clipped if the amplitude of the luma is too high. When this bit is
set (0), this control is disabled.
Hue Adjust Control (MR72)
This bit is used to enable hue adjustment on the composite and
chroma output signals of the ADV7194. When this bit is set (1),
the hue of the color is adjusted by the phase offset described in
the Hue Adjust Control Register. When this bit is set (0), hue
adjustment is disabled.
Brightness Enable Control (MR73)
This bit is used to enable brightness control on the ADV7194.
The actual brightness level is programmed in the Brightness
Control Register. This value or set-up level is added to the scaled
Y data. When this bit is set (1), brightness control is enabled.
When this bit is set (0), brightness control is disabled.
Sharpness Filter Enable (MR74)
This bit is used to enable the sharpness control of the luminance
signal on the ADV7194 (Luma Filter Select has to be set to
Extended, MR04–MR02 = 100). The various responses of the
filter are determined by the Sharpness Control Register. When
this bit is set 1, the luma response is altered by the amount
described in the Sharpness Control Register. When this bit is
set 0, the sharpness control is disabled. See Internal Filter
Response section.
CSO_HSO
Output Control (MR75)
This bit is used to determine whether
HSO
or
CSO
TTL output
signal is output at the
CSO_HSO
pin. If this bit is set 1, then
the
CSO
TTL signal is output. If this bit is set 0, the
HSO
TTL
signal is output.
TTX Input/ CLAMP–
VSO
Output Control (MR76)
This bit controls whether Pin 62 is configured as an output or as
an input pin. A 1 selects Pin 62 to be an output for CLAMP or
VSO
functionality. A 0 selects this pin as a TTX input pin.
CLAMP/
VSO
Select Control (MR77)
This bit is used to select the functionality of Pin 62. Setting this
bit to 1 selects CLAMP as the output signal. A 0 selects
VSO
as the output signal. Since this pin is also shared with the TTX
functionality, TTX Input/ CLAMP–
VSO
Output has to be set
accordingly (MR76).
MR67
MR66
MR65
MR64
MR63
MR62
MR61
MR60
0
1
ENABLED
DISABLED
MR60
POWER-UP SLEEP
MODE CONTROL
0
1
ENABLED
DISABLED
MR61
PLL ENABLE
CONTROL
ZERO MUST
BE WRITTEN
TO THESE BITS
MR64 MR63 MR62
FIELD COUNTER
MR67 MR66 MR65
Figure 61. Mode Register 6, MR6
MR77
MR76
MR75
MR74
MR73
MR72
MR71
MR70
0
1
DISABLE
ENABLE
MR74
SHARPNESS FILTER
ENABLE
0
1
VSO
OUTPUT
CLAMP OUTPUT
MR77
CLAMP/
VSO
OUTPUT CONTROL
0
1
DISABLE
ENABLE
MR70
COLOR CONTROL
ENABLE
CSO_HSO
OUTPUT CONTROL
MR75
0
1
HSO
OUT
CSO
OUT
0
1
DISABLE
ENABLE
MR72
HUE ADJUST
CONTROL
0
1
DISABLE
ENABLE
MR73
BRIGHTNESS
ENABLE CONTROL
0
1
DISABLE
ENABLE
MR71
LUMA SATURATION
CONTROL
MR76
0
1
TTX INPUT/CLAMP/
VSO
OUTPUT CONTROL
TXX INPUT
CLAMP/
VSO
OUTPUT
Figure 62. Mode Register 7, MR7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7194KSTZ 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7194KSTZ 制造商:Analog Devices 功能描述:TV / Video IC
ADV7195 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
ADV7195KS 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk
ADV7195KST 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
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