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參數(shù)資料
| 型號： | ADV3205JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 16X16 100LQFP |
| 標準包裝： | 1 |
| 功能： | 交叉點開關 |
| 電路： | 1 x 16:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±5.5 V |
| 電流 - 電源： | 45mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
Data Sheet
ADV3205
Rev. 0 | Page 15 of 20
APPLICATIONS INFORMATION
The ADV3205 has two options for changing the programming of
the crosspoint matrix. In the first option, a serial word of 80 bits can
be provided that updates the entire matrix in one serial operation.
The second option allows for changing the programming of a
single output via a parallel interface. The serial option requires
fewer signals but more time (clock cycles) for changing the
programming, whereas the parallel programming technique
requires more signals, but can change a single output at a time,
and requires fewer clock cycles to complete programming.
SERIAL PROGRAMMING
The serial programming mode uses the device pins: CE, CLK,
DATA IN, UPDATE, and SER/PAR. The first step is to assert a
low on SER/PAR to enable the serial programming mode. CE
for the chip must be low to allow data to be clocked into the
device. The CE signal can be used to address an individual
device when devices are connected in parallel.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as defined by
the shifting data.
The data at DATA IN is clocked in at every down edge of CLK. A
total of 80 bits must be shifted into the shift register via the DATA
IN input to complete the programming. For each of the 16 outputs,
there are four bits (D0 to D3) that determine the source of its
input followed by one bit (D4) that determines the enabled state
of the output. If D4 is low (output disabled), the four associated
bits (D0 to D3) do not matter because no input is switched to
that output.
The most significant output address data is shifted into the shift
register first, following in sequence until the least significant
output address data is shifted in. At this point UPDATE can be
taken low, which causes the programming of the device according
to the data that was just shifted in. The UPDATE registers are
asynchronous, and when UPDATE is low (and CE is low), the
registers are transparent.
When more than one ADV3205 device is serially programmed in a
system, the DATA OUT signal from one device can be connected
to the DATA IN of the next device to form a serial chain. Connect
all of the CLK, CE, UPDATE, and SER/PAR pins in parallel and
operate them as previously described. The serial data is input to
the DATA IN pin of the first device of the chain, and it ripples
through to the last. Therefore, the data for the last device in the
chain should come at the beginning of the programming sequence.
The length of the programming sequence is 80 bits times the
number of devices in the chain.
PARALLEL PROGRAMMING
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows for the modification of a
single output at a time. Because this takes only one CLK/UPDATE
cycle, significant time savings can be realized by using parallel
programming.
One important consideration in using parallel programming is
that the RESET signal does not reset all registers in the
.
When taken low, the
RESET signal only sets each output to the
disabled state. This is helpful during power-up to ensure that
two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device generally
contain random data, even though the RESET signal has been
asserted. If parallel programming is used to program one output,
that output is properly programmed but the rest of the device
has a random program state depending on the internal register
content at power-up. Therefore, when using parallel programming,
it is essential that all outputs be programmed to a desired state
after power-up. This ensures that the programming matrix is
always in a known state. From then on, parallel programming
can be used to modify a single output at a time.
In similar fashion, if both CE and UPDATE are taken low after
initial power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent the crosspoint
from being programmed into an unknown state, do not apply
low logic levels to both CE and UPDATE after power is initially
applied. Programming the full shift register one time to a desired
state, by either serial or parallel programming after initial power-up,
eliminates the possibility of programming the matrix to an
unknown state.
To change the output’s programming via parallel programming,
take SER/PAR and UPDATE high and take CE low. The CLK
signal should be in the high state. Put the 4-bit address of the
output to be programmed on the A0 to A3 pins. The first four
data bits (D0 to D3) should contain the information that identifies
the input that is programmed to the output that is addressed.
The fifth data bit (D4) determines the enabled state of the output. If
D4 is low (output disabled), the data on D0 to D3 does not matter.
After the desired address and data signals are established, they
can be latched into the shift register by a high-to-low transition
of the CLK signal. The matrix is not programmed, however, until
the UPDATE signal is taken low. It is thus possible to latch in
new data for several or all of the outputs first via successive
negative transitions of CLK while UPDATE is held high and then
have all of the new data take effect when UPDATE goes low.
Use this technique when programming the device for the first
time after power-up when using parallel programming.
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