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參數(shù)資料
| 型號： | ADV3205JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 16X16 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 16:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±5.5 V |
| 電流 - 電源： | 45mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
ADV3205
Data Sheet
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
The ADV3205 is a gain-of-two crosspoint array with 16 outputs,
each of which can be connected to any one of 16 inputs.
Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a
16-to-1 multiplexer. Each of the 16 rows of transconductance
stages are wired in parallel to the 16 input pins, for a total array
of 256 transconductance stages. Decoding logic for each output
selects one (or none) of the transconductance stages to drive the
output stage. The transconductance stages are NPN input differential
pairs, sourcing current into the folded cascode output stage.
The compensation networks and emitter follower output buffers
are in the output stage. Voltage feedback sets the gain at +2.
The ADV3205 can drive reverse-terminated video loads,
swinging ±3.0 V into 150 Ω. Disabling unused outputs
and transconductance stages minimizes on-chip power
consumption.
Features of the ADV3205 facilitate the construction of larger
switch matrices. The unused outputs can be disabled, leaving
only a feedback network resistance of 4 kΩ on the output. This
allows multiple ICs to be bused together, provided the output
load impedance is greater than the minimum allowed values.
Because no additional input buffering is necessary, high input
resistance and low input capacitance are easily achieved without
additional signal degradation.
The ADV3205 inputs have a unique bias current compensation
scheme that overcomes a problem common to transconductance
input array architectures. Typically, input bias current increases
as more and more transconductance stages connected to the same
input are turned on. Anywhere from 0 to 16 transconductance
stages can be sharing one input pin, so there is a varying amount of
bias current supplied through the source impedance driving the
input. The ADV3205 samples and cancels the input bias current
contributions from each transconductance stage so that the
residual bias current is nominally zero, regardless of the number
of enabled inputs.
The ADV3205 contains internal crosstalk isolation clamps that
have variable bias levels. These levels were chosen to allow the
necessary input range to accommodate the full output swing
with a gain of +2. Overdriving the inputs beyond the linear
range of the device eventually forward biases these clamps,
increasing the power dissipation. The valid input range is ±1.5 V.
When outputs are disabled and being driven externally, the
voltage applied to them should not exceed the valid input swing
range for the ADV3205.
A flexible TTL-compatible logic interface simplifies the
programming of the matrix. Either parallel or serial loading
into a first rank of latches programs each output. A global latch
simultaneously updates all outputs. In serial mode, a serial data out
pin (DATA OUT) allows devices to be daisy chained together
for single pin programming of multiple ICs. A power-on reset
function can be implemented to avoid bus conflicts by disabling
all outputs.
The digital logic requires 5 V on the DVCC pin with respect to
DGND. Internal ESD protection diodes require that the DGND
and AGND pins be at the same potential.
SHORT-CIRCUIT OUTPUT CONDITIONS
Although there is short-circuit current protection on the ADV3205
outputs, the short-circuit output current can reach levels that
can result in device failure. Do not operate the ADV3205 with a
sustained short to ground on any of its outputs.
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