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參數(shù)資料
| 型號(hào)： | ADV3205JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 16X16 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 16:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±5.5 V |
| 電流 - 電源： | 45mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
Data Sheet
ADV3205
Rev. 0 | Page 19 of 20
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced cross-
talk. However, significant current can flow through the input
termination resistors and the loops that drive them. Thus, the
PCB on the input side can contribute to magnetically coupled
crosstalk.
From a circuit standpoint, the input crosstalk mechanism is
similar to a capacitor coupling to a resistive load. For low
frequencies, the magnitude of the crosstalk is given by
|XT| = 20log10[(RSCM) × s]
where:
RS is the source resistance.
CM is the mutual capacitance between the test signal circuit and
the selected circuit.
s is the Laplace transform variable.
From the previous equation, it can be observed that this crosstalk
mechanism has a high-pass nature; it can also be minimized by
reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is driven
from a 75 Ω terminated cable, the input crosstalk can be reduced
by buffering this signal with a low output impedance buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the ADV3205 is specified with excellent
differential gain and phase when driving a standard 150 Ω video
load, the crosstalk is higher than the minimum obtainable due
to the high output currents. These currents induce crosstalk via
the mutual inductance of the output pins and bond wires of the
From a circuit standpoint, this output crosstalk mechanism is
similar to a transformer with a mutual inductance between the
windings that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
|XT| = 20log10(Mxy × s/RL)
where:
Mxy is the mutual inductance of Output X to Output Y.
RL is the load resistance on the measured output.
This crosstalk mechanism can be minimized by keeping the
mutual inductance low and increasing RL. The mutual inductance
can be kept low by increasing the spacing of the conductors and
minimizing their parallel lengths.
PCB Layout
Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing, and
supply bypassing.
The packaging of the ADV3205 is designed to keep the crosstalk
to a minimum. Each input is separated from every other input
by an analog ground pin. Directly connect all AGND pins to the
ground plane of the circuit board. These ground pins provide
shielding, low impedance return paths, and physical separation
for the inputs. All of these help to reduce crosstalk.
Each output is separated from its two neighboring outputs by an
analog supply pin of one polarity or the other. Each of these analog
supply pins provides power to the output stages of only the two
nearest outputs. These supply pins provide shielding, physical
separation, and a low impedance supply for the outputs. Individual
bypassing of each of these supply pins with a 0.1 μF chip capacitor
directly to the ground plane minimizes high frequency output
crosstalk via the mechanism of shared common impedances.
Each output also has an on-chip compensation capacitor that is
individually tied to the nearby analog ground pins. This technique
reduces crosstalk by preventing the currents that flow in these paths
from sharing a common impedance on the IC and in the package
pins. Directly connect these AGND pins to the ground plane.
There are separate digital (logic) and analog supplies. DVCC
must be at 5 V to be compatible with the 5 V CMOS and TTL
logic. AVCC and AVEE can range from ±5 V to ±12 V, depending
on the application.
Locally decouple each power supply pin (or group of adjacent
power supply pins) with a 0.1 μF capacitor. Use a 10 μF capacitor to
decouple power supplies as they come onto the board.
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