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參數(shù)資料
| 型號： | ADUC848BCPZ8-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH W/16BIT ADC 56-CSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x16b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 27 of 108
Signal Chain Overview (Chop Enabled, CHOP = 0)
With the CHOP bit = 0 (see the ADCMODE SFR bit designa-
tions in Table 24), the chopping scheme is enabled. This is the
default condition and gives optimum performance in terms of
offset errors and drift performance. With chop enabled, the
available output rates vary from 5.35 Hz to 105 Hz (SF = 255
and 13, respectively). A typical block diagram of the ADC input
channel with chop enabled is shown in Figure 12.
The sampling frequency of the modulator loop is many times
higher than the bandwidth of the input signal. The integrator in
the modulator shapes the quantization noise (which results
from the analog-to-digital conversion) so that the noise is pushed
toward one-half of the modulator frequency. The output of the
Σ-Δ modulator feeds directly into the digital filter. The digital
filter then band-limits the response to a frequency significantly
lower than one-half of the modulator frequency. In this manner,
the 1-bit output of the comparator is translated into a band
limited, low noise output from the ADCs.
The ADC filter is a low-pass Sinc3 or (sinx/x)3 filter whose
primary function is to remove the quantization noise introduced
at the modulator. The cutoff frequency and decimated output
data rate of the filter are programmable via the Sinc filter word
loaded into the filter (SF) register (see Table 28). The complete
signal chain is chopped, resulting in excellent dc offset and
offset drift specifications and is extremely beneficial in applica-
tions where drift, noise rejection, and optimum EMI rejection
are important.
With chop enabled, the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc3 filter, therefore,
have a positive offset and a negative offset term included. As a
result, a final summing stage is included so that each output
word from the filter is summed and averaged with the previous
filter output to produce a new valid output result to be written
to the ADC data register. Programming the Sinc3 decimation
factor is restricted to an 8-bit register called SF (see Table 28),
the actual decimation factor is the register value times 8.
Therefore, the decimated output rate from the Sinc3 filter (and
the ADC conversion rate) is
MOD
ADC
f
SF
f
×
=
8
1
3
1
where:
fADC is the ADC conversion rate.
SF is the decimal equivalent of the word loaded to the filter
register.
fMOD is the modulator sampling rate of 32.768 kHz.
The chop rate of the channel is half the output data rate:
ADC
CHOP
f
×
=
2
1
outputs alternately contain +VOS and VOS, where VOS is the
respective channel offset.
SINC3 FILTER
PGA
3
× (8 × SF)
S-D
MOD
FADC
DIGITAL
OUTPUT
ANALOG
INPUT
MUX
BUF
AIN + VOS
AIN – VOS
FMOD
XOR
2
FCHOP
FIN
04741-013
S-D
Figure 12. Block Diagram of the ADC Input Channel with Chop Enabled
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