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參數(shù)資料
| 型號： | ADUC848BCPZ8-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH W/16BIT ADC 56-CSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x16b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 24 of 108
SPECIAL FUNCTION REGISTERS (SFRs)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph-
erals. A block diagram showing the programming model of the
ADuC845/ADuC847/ADuC848 via the SFR area is shown in
All registers except the program counter (PC) and the four
general-purpose register banks reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
62-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
8051-
COMPATIBLE
CORE
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
SENSOR
CURRENT SOURCES
12-BIT DAC
SERIAL I/O
WDT
PSM
TIC
PWM
S-D ADC
4-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
256 BYTES RAM
2kBYTES XRAM
04741-011
Figure 11. Programming Model
Accumulator SFR (ACC)
ACC is the accumulator register, which is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions usually refer to the
accumulator as A.
B SFR (B)
The B register is used with the accumulator for multiplication
and division operations. For other instructions, it can be treated
as a general-purpose scratch pad register.
Data Pointer (DPTR)
The data pointer is made up of three 8-bit registers: DPP (page
byte), DPH (high byte), and DPL (low byte). These provide
memory addresses for internal code and data memory access.
The DPTR can be manipulated as a 16-bit register (DPTR =
DPH, DPL), although INC DPTR instructions automatically
carry over to DPP, or as three independent 8-bit registers (DPP,
DPH, DPL).
The ADuC845/ADuC847/ADuC848 support dual data
pointers. See the Dual Data Pointers section.
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer, which is used to hold an
internal RAM address called the top of the stack. The SP register
is incremented before data is stored during PUSH and CALL
executions. Although the stack can reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
As mentioned earlier, the parts offer an extended 11-bit stack
pointer. The three extra bits needed to make up the 11-bit stack
pointer are the three LSBs of the SPH byte located at B7H. To
enable the SPH SFR, the EXSP (CFG84x.7) bit must be set;
otherwise, the SPH SFR can be neither written to nor read from.
Program Status Word (PSW)
The PSW SFR contains several bits that reflect the current
status of the CPU as listed in Table 5.
SFR Address:
D0H
Power-On Default:
00H
Bit Addressable:
Yes
Table 5. PSW SFR Bit Designations
Bit No.
Name
Description
7
CY
Carry Flag.
6
AC
Auxiliary Carry Flag.
5
F0
General-Purpose Flag.
4, 3
RS1, RS0
Register Bank Select Bits.
RS1
RS0
Selected Bank
0
1
0
2
1
3
2
OV
Overflow Flag.
1
F1
General-Purpose Flag.
0
P
Parity Bit.
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